3803 datasheet(11/26 Pages) RENESAS

11 / 26 page

Rev.4.01

Date: Jul.02.08

REJ99B0048-0401

6. Flash Memory ID code and ROM Code Protect

In the 3803H/3803L Groups Flash memory version, ID codes are assigned to addresses FFD to FFDA16, and ROM code protect is

assigned to address FFDB16. Please note that these addresses are included in the user ROM area. The data of these addresses must be

set to programming data before programming.

7. QzROM ROM Code Protect

In the QzROM version, ROM code protect is assigned to address FFDB16. If you select write to protect bit with a serial programmer or

select programming by Renesas Technology before shipment to enable protect, “0016” (all area protected) or “FE16” (protect area 1

protected) is written into this address. Otherwise, “FF16” is written to this address. The address cannot be used by user programs.

8. Flash Memory Control Registers

- In the 3803H/3803L Group Flash memory version, Flash Memory control registers 0 to 2 are assigned to addresses 0FE0 to 0FE216.

- In the 3803 Group Flash memory version, Flash Memory control register is assigned to address 0FFE16 and Flash command register is

assigned to address 0FFF16.

- In the Mask ROM/QzROM versions, nothing is allocated to these addresses, so writing can be performed to them.

When read, their values are undefined.

9. Program/Erase Power Source

The program/erase power source voltage as well as the absolute maximum ratings of the pins differ for each product. Ensure that the

specified programmer is connected to your product to prevent a voltage that exceeds the ratings from being applied to the pins.

10. Program/Erase Mode

In the QzROM version, only serial I/O mode is available in program/erase mode. When requesting off-board programming, please prepare

a separate board for that purpose. MCU units for serial programming may also be available from the programmer manufacturer.

11. Time until Flash Memory can Operate after Returning from Stop Mode

In the 3803H/3803L Group Flash memory version, the internal power supply circuit is switched to low power consumption mode for

reducing consumption current during STP instruction. Although the internal power supply circuit is automatically switched to thenormal

operation mode when returning from the STP instruction, a certain time is required until the flash memory can operate after the power

supply restarts. Therefore, set 100

μsec or more by the oscillation stabilization time setting function after the STP instruction which uses

timer 1 is released.

Replacement Notes (2)

3803 Datasheet(PDF) 11 Page - Renesas Technology Corp