LPC1102 datasheet(15/39 Pages) NXP

15 / 39 page

LPC1102

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Product data sheet

Rev. 3 — 18 April 2011

15 of 39

NXP Semiconductors

LPC1102

32-bit ARM Cortex-M0 microcontroller

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update.

3. Running an application with level CRP3 selected fully disables any access to the chip

via the SWD pins.

Remark: The LPC1102 does not provide an ISP entry pin to be monitored at reset. For all

three CRP levels, the user’s application code must provide a flash update mechanism

which reinvokes ISP by defining a user-selected PIO pin for ISP entry.

7.15.5 APB interface

The APB peripherals are located on one APB bus.

7.15.6 AHBLite

The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main

static RAM, and the Boot ROM.

7.15.7 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs

serve as external interrupts (see Section 7.15.1).

7.16 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four

breakpoints and two watchpoints is supported.

Remark: Care must be taken when using the SPI because the SPI clock SCK and the

serial wire debug clock SWCLK share the same pin on the WLCSP16 package. Once the

SPI is enabled, the serial wire debugger is no longer available.

CAUTION

If Code Read Protection of any level (CRP1, CRP2 or CRP3) is selected, no future factory

testing can be performed on the device.

LPC1102 Datasheet(PDF) 15 Page - NXP Semiconductors