PCA8576D datasheet(21/42 Pages) NXP

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PCA8576D

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Product data sheet

Rev. 1 — 4 April 2011

21 of 42

NXP Semiconductors

PCA8576D

Automotive 40 x 4 LCD segment driver for low multiplex rates

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I2C-bus is shown in Figure 15.

7.16.5 I2C-bus controller

The PCA8576D acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or

transmit data to an I2C-bus master receiver. The only data output from the PCA8576D are

the acknowledge signals of the selected devices. Device selection depends on the

I2C-bus slave address, on the transferred command data and on the hardware

subaddress.

In single device applications, the hardware subaddress inputs A0, A1 and A2 are normally

tied to VSS which defines the hardware subaddress 0. In multiple device

applications A0, A1 and A2 are tied to VSS or VDD in accordance with a binary coding

scheme such that no two devices with a common I2C-bus slave address have the same

hardware subaddress.

7.16.6 Input filters

To enhance noise immunity in electrically adverse environments, RC low-pass filters are

provided on the SDA and SCL lines.

7.16.7 I2C-bus protocol

Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCA8576D.

The PCA8576D slave address is illustrated in Table 7.

Fig 15. Acknowledgement of the I2C-bus

mbc602

START

condition

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from

master

Table 7.

I2C slave address byte

Slave address

Bit

MSB

LSB

SA0

R/W

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