1.5Msps, Single-Supply, Low-Power, True-

Differential, 10-Bit ADCs with Internal Reference

______________________________________________________________________________________

13

edge. When using CPOL = 0 and CPHA = 0 or CPOL = 1

and CPHA = 1, the data is clocked into the µP on the

following rising edge. When using CPOL = 0 and CPHA

= 1 or CPOL = 1 and CPHA = 0, the data is clocked

into the µP on the next falling edge. See Figure 11 for

connections and Figures 12 and 13 for timing. See the

Timing Characteristics section to determine the best

mode to use.

QSPI

Unlike SPI, which requires two 1-byte reads to acquire

the 10 bits of data from the ADC, QSPI allows the mini-

mum number of clock cycles necessary to clock in the

data. The MAX1077/MAX1079 require 16 clock cycles

from the µP to clock out the 10 bits of data. Figure 14

shows a transfer using CPOL = 1 and CPHA = 1. The

conversion result contains three zeros, followed by the

10 data bits, 2 sub-bits, and a trailing zero with the data

in MSB-first format.

DSP Interface to the TMS320C54_

The MAX1077/MAX1079 can be directly connected

to the TMS320C54_ family of DSPs from Texas

Instruments, Inc. Set the DSP to generate its own

clocks or use external clock signals. Use either the

standard or buffered serial port. Figure 15 shows the

simplest interface between the MAX1077/MAX1079 and

the TMS320C54_, where the transmit serial clock

(CLKX) drives the receive serial clock (CLKR) and

SCLK

DOUT

916

8

1

D0

D9

D8

D6

D5

D4

D3

D2

D1

D7

HIGH-Z

HIGH-Z

CNVST

S1

S0

Figure 13. SPI/MICROWIRE Serial-Interface Timing—Continuous Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)

0

0

0

D9D8D7

D6D5

D4D3

D2D1

D0

S1

S0

0

DOUT

SCLK

CNVST

0

1

1

14

16

Figure 12. SPI/MICROWIRE Serial-Interface Timing—Single Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)

Figure 14. QSPI Serial-Interface Timing—Single Conversion (CPOL = 1, CPHA = 1)

SCLK

DOUT

CNVST

16

S0

S1

D9

D8

D4

D5

D6

D3

D2

D1

D0

HIGH-Z

D7

HIGH-Z

2