No. 5350-4/5

VP553

Sample Thermal Design for the VP553

Here we consider the case where such a monitor is to be operated at ambient temperatures up to Ta = 60°C and at a

maximum frequency of f = 100 MHz (clock).

As mentioned previously, the chips with the maximum loss will be transistors 3 and 4 in the emitter-follower stage.

Equation (5) follows from deriving that value from the figure below and equation (3).

However, the actual usage conditions include a blanking period. If we calculate the power during this period

for transistors 3 and 4 will be:

If the blanking period is 20% of the total, from the data of equation (5) and formula (6) we see that the loss in transistors

3 and 4 will be:

Next, applying the value of

θj–c to equation (7), shows ∆Tj to be:

∆Tj = 1.28 × 35 ≈ 45 [°C]

Since

∆Tj ≤ 50°C, it suffices to only consider the Tc ≤ 100°C condition in the thermal design. That is, in the thermal

design we design

θh so that Tc will be under 100°C when Pd (total) = Pd (1ch) × 3 for the time when all three channels

are operating at their maximum levels.

∆Tc will be: ∆Tc = 100 – 60 = 40°C

θh = ∆Tc ÷ Pd (total) = 40 ÷ {(6.2 × 0.8 + 2.2 × 0.2) × 3} = 2.5

Thus:

θh = 2.5°C/W

In actual use, due to the actual ambient temperature, the operating conditions, and other factors, it will be possible to use

a heat sink smaller than the one required by the above design. Users should design an optimal heat sink using the data

presented above and their actual conditions.

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