Data Sheet Rev. 1.2

13

2003-06-02

TLE 6363

Watchdog Operation

The watchdog uses one hundred of the oscillator’s clock signal period as a timebase,

defined as the watchdog cycle time

t

After power-on, the reset output signal at the RO pin (microcontroller reset) is kept LOW

for the reset delay time

t

at RO the device starts the closed window time

t

this window is interpreted as a pretrigger failure according to the figures shown below.

After the closed window the open window with the duration

t

window lasts at minimum until the trigger process has occurred, at maximum

t

32 cycles.

A HIGH to LOW transition of the watchdog trigger signal on pin WDI is taken by a trigger.

To avoid wrong triggering due to parasitic glitches two HIGH samples followed by two

LOW samples (sample period

t

appears at the watchdog input pin WDI during the open window or a power up/down

occurs, the watchdog window signal is reset and a new closed window follows.

A reset is generated (RO goes LOW) if there is no trigger pulse during the open window

or if a pretrigger occurs during the closed window. This reset happens after 64 cycles

after the latest valid closed window start time and lasts for further 64 cycles.

The triggering is correct also, if the first three samples (two HIGH one LOW) of the trigger

pulse at pin WDI are inside the closed window and only the fourth sample (the second

LOW sample) is taken in the open window.

In addition to the microcontroller reset signal RO the device generates a system enable

signal at pin SEN. If RO is HIGH the system enable goes active HIGH with the first valid

watchdog trigger pulse at pin WDI. The SEN output goes LOW immediately if a

pretrigger, a missing trigger or a power down reset occurs.