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XC164CS-8F Datasheet(PDF) 21 Page - Infineon Technologies AG

Part # XC164CS-8F
Description  16-Bit Single-Chip Microcontroller with C166SV2 Core
PDF  80 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

XC164CS-8F Datasheet(HTML) 21 Page - Infineon Technologies AG

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XC164CS
Derivatives
Functional Description
Data Sheet
19
V2.3, 2006-08
bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7,
RH7) so-called General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,
any location in the DPRAM is bitaddressable.
1024 bytes (2
× 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC166 Family. Therefore, they should
either not be accessed, or written with zeros, to ensure upward compatibility.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 12 Mbytes (approximately, see Table 3) of external RAM and/or ROM can
be connected to the microcontroller.
Table 3
XC164CS Memory Map1)
1) Accesses to the shaded areas generate external bus accesses.
Address Area
Start Loc. End Loc.
Area Size2)
2) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.
Notes
Flash register space
FF’F000H
FF’FFFFH
4 Kbytes
Flash only3)
3) Not defined register locations return a trap code.
Reserved (Acc. trap)
F8’0000H
FF’EFFFH < 0.5 Mbytes Minus Flash register
space
Reserved for PSRAM
E0’0800H
F7’FFFFH
< 1.5 Mbytes Minus PSRAM
Program SRAM
E0’0000H
E0’07FFH
2 Kbytes
Maximum
Reserved for program
memory
C2’0000H
DF’FFFFH < 2 Mbytes
Minus Flash/ROM
Program Flash/ROM
C0’0000H
C1’FFFFH 128 Kbytes
4)
4) Depends on the respective derivative. The derivatives are listed in Table 1.
Reserved
BF’0000H
BF’FFFFH 64 Kbytes
–
External memory area 40’0000H
BE’FFFFH < 8 Mbytes
Minus reserved
segment
External IO area5)
5) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
peripherals properly.
20’0800H
3F’FFFFH
< 2 Mbytes
Minus TwinCAN
TwinCAN registers
20’0000H
20’07FFH
2 Kbytes
–
External memory area 01’0000H
1F’FFFFH
< 2 Mbytes
Minus segment 0
Data RAMs and SFRs 00’8000H
00’FFFFH
32 Kbytes
Partly used4)
External memory area 00’0000H
00’7FFFH
32 Kbytes
–



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