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TUSB8040 Datasheet(PDF) 16 Page - Texas Instruments |
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TUSB8040 Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 27 page ![]() TUSB8040 SLLSE42C – SEPTEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Table 3-13. Bit Descriptions – Device Configuration Register (continued) BIT FIELD NAME ACCESS DESCRIPTION u1u2Disable RW U1 U2 Disable When this bit is set, the TUSB8040 will not initiate or accept any U1 or U2 requests on any port, upstream or downstream, unless it receives or sends a Force_LinkPM_Accept LMP command. After receiving or sending a FLPMA LMP command, the TUSB8040 will continue to enable U1 or U2 until it gets a power on reset or is disconnected on its 5 upstream port. This bit is loaded at the deassertion of reset with the value of the SDA_SMDAT terminal. When the TUSB8040 is in I2C mode, the TUSB8040 loads this bit from the contents of the EEPROM. When the TUSB8040 is in SMBUS mode, the value may be over-written by a SMBUS host. 4 portIndz R Port Indicator Status. This bit is always 1. 3 ganged R Ganged. This bit is always 1. fullPwrMgmtz RW Full Power Management. This bit is loaded at the de-assertion of reset with the value of the FULLPWRMGMTz_SMBA1 terminal. 2 When the TUSB8040 is in I2C mode, the TUSB8040 loads this bit from the contents of the EEPROM. When the TUSB8040 is in SMBUS mode, the value may be over-written by an SMBus host. 1:0 RSVD RO Reserved. This field is reserved and returns 0 when read. 3.3.7 Battery Charging Support Register Table 3-14. Register Offset 6h BIT NO. 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 X X X X Table 3-15. Bit Descriptions – Battery Charging Support Register BIT FIELD NAME ACCESS DESCRIPTION 7:4 RSVD RO Reserved. Read only, returns 0 when read. Battery Charger Support. The bits in this field indicate whether the downstream port implements the charging port features. A value of 0 indicates the port does not implement the charging port features. A value of 1 indicates the port does support the charging port features. Each bit corresponds directly to a downstream port, i.e. batEn0 corresponds to downstream port 0 (physical port 1). 3:0 batEn[3:0] RW The default value for these bits are loaded at the de-assertion of reset with the value of the PWRON0z_BATEN0 for all ports enabled in the configuration: Four-port hub - bateEn[3:0] defaults to wxyzb, where w, x, y and z are the value of PWRON0z_BATEN0 when reset is de-asserted. When in I2C/SMBus mode the bits in this field corresponding to the enabled ports per used[3:0] may be over-written by EEPROM contents or by an SMBus host. 3.3.8 Device Removable Configuration Register Table 3-16. Register Offset 7h BIT NO. 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 16 FUNCTIONAL DESCRIPTION Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB8040 |
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