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LX1689 Datasheet(PDF) 2 Page - Microsemi Corporation |
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LX1689 Datasheet(HTML) 2 Page - Microsemi Corporation |
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2 / 14 page ![]() Microsemi Integrated Products 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 2 Copyright © 2000 Rev. 1.1, 2006-02-27 LX1689 Third Generation CCFL Controller PRODUCTION DATA SHEET TM ® ABSOLUTE MAXIMUM RATINGS Supply Voltage (V_BATT)................................................................................................. 30V Digital Input (ENABLE)..................................................................................... -0.3V to 7V Analog Inputs Transient Peak (I_SNS, OC_SNS, OV_SNS)..............................-25V to +25V Analog Inputs (BRITE_IN, EA_IN).................................................................. -0.3V to 5.5V Digital Inputs (DIM_CLK,DIM_MODE, DIV_248) ......................................... -0.3V to 5.5V Digital Output (AOUT, BOUT) .................................................................-0.3V to VDD_P +0.5V Analog Outputs (BRITE_C, I_R, BRITE_OUT, BRITE_R, EA_OUT) ...-0.3V to VDD_A_ +0.5V Storage Temperature Range ........................................................................ -65°C to 150°C Maximum Operating Junction Temperature...............................................................150°C RoHS / Pb-free Peak Package Solder Reflow Temperature (40 second maximum exposure).....................................................................260°C (+0,-5) Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of specified terminal. PACKAGE PIN OUT A OUT V_BATT OV_SNS I_SNS ENABLE VDD_P BRITE_R DIM_MODE BRITE_IN DIM_CLK OC_SNS EA_IN BRITE_C GND VDD_A B OUT DIV_248 EA_OUT BRITE_OUT I_R 1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 PW PACKAGE (Top View) RoHS / Pb-free 100% Matte Tin Lead Finish TH ERMAL DATA PW Plastic TSSOP 20-Pin THERMAL RESISTANCE-JUNCTION TO AMBIENT, θ JA 144°C/W Junction Temperature Calculation: TJ = TA + (PD x θJA). The θ JA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. FUNCTIONAL PIN DESCRIPTION PIN NAME DESCRIPTION GND Ground VDD_P Power VDD_P Supply Output. This output pin is used to connect an external capacitor to stabilize and filter the on chip VDD_P LDO regulator. The input of the LDO is the switched V_BATT supply. LDO output is normally 5.3V and is used only to drive the output buffers at AOUT and BOUT. The external capacitor will be a 100 to 1000nF ceramic dielectric. Up to 5mA DC additional load may be imposed by external circuitry. External load must be reduced if the combination of output current and input voltage exceeds power dissipation capability of the die. AOUT A buffer N-FET driver output. The pin includes a internal 10K pull down resistor. VDD_A Analog VDD_A Supply Output. This output pin is used to connect an external capacitor to stabilize and filter the on chip VDD_A LDO regulator. The input of the LDO is the switched V_BATT supply. LDO output is normally 2.95V and is used to drive all circuitry except the output buffers at AOUT and BOUT. Average internal load is 6mA. Up to 5mA DC additional load may be imposed by external circuitry. External load must be reduced if the combination of output current and input voltage exceeds power dissipation capability of the die. The external capacitor will be a 100 to 1000nF ceramic dielectric type. BOUT B buffer N-FET driver output. The pin includes a internal 10K pull down resistor. V_BATT Voltage Input, 3 to 28V input range. V_BATT is switched (see ENABLE) to remove power from chip. Two LDO regulators follow the switch, one generates VDD_P (see VDD_P) and the other VDD_A (see VDD_A). Care must be taken in power distribution design to minimize transients and noise coupling from the VDD_P output to the VDD_A output. The external capacitor will be a 100 to 1000nF ceramic dielectric type. |
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