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SZMD03C Datasheet(PDF) 2 Page - SeCoS Halbleitertechnologie GmbH

Part # SZMD03C
Description  Transient Voltage Suppressors for ESD Protection
PDF  2 Pages
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Manufacturer  SECOS [SeCoS Halbleitertechnologie GmbH]
Direct Link  http://www.secosgmbh.com
Logo SECOS - SeCoS Halbleitertechnologie GmbH

SZMD03C Datasheet(HTML) 2 Page - SeCoS Halbleitertechnologie GmbH

  SZMD03C Datasheet HTML 1Page - SeCoS Halbleitertechnologie GmbH SZMD03C Datasheet HTML 2Page - SeCoS Halbleitertechnologie GmbH  
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Elektronische Bauelemente
SZMD03C
24W, 3 V
Transient Voltage Suppressors
for ESD Protection (Uni-directional)
01-June-2002 Rev. A
Page 2 of 2
http://www.SeCoSGmbH.com/
Any changes of specification will not be informed individually.
RATINGS AND CHARACTERISTICS CURVES
Applications Information
Device Connection Options
The SZMD series is designed to protect one
bi-directional or two uni-directional data or l/O lines
operating at 3 volts.Connection options are as
follows:
‧Bidirectional:Pin 1 is connected to the data line and
pin 2 is connected to ground (Since the device lls
symmetrical,these conmtions may be re- Ver3ed).For
best results,the ground connection should be made
directly to a ground plane on the board.The path
length should be kept as short as possible to minimize
parasitic inductance-Pin 3 is not
connected. ‧Unidirectional:Data lines are connected
to pin1 and pin2.Pin 3 is connected to ground.For
best results,this pin should be connected directly to a
ground plane on the board.The path lengh should be
kept as short as possible to minimize parasitic
inductance.
Circuit Board Layout Recommendations
for suppres- sion of ESD. Good circuit board layout is
critical for the suppression of fast rise-time transients
such as ESD.The following guidelines are
recommended (Refer to application note Sl99.01 for
more detailed information): ‧Place the TVS near the
input terminals or connec- tors to restrict transient
coupling. ‧Minimize the path length between the
TVS and the protected line. ‧Minimize all conductive
loops including power and ground loops. ‧The ESD
transient return path toground should be kept as short
as possible. ‧Never run critical signals near board
edges
‧Use ground planes whenever possib|e.
0
10
20
30
40
50
60
70
80
90
100
110
0
5
10
15
20
25
30
Time (us)
e
-t
td = IPP /2
Wave form
Paramete rs:
tr = 8 s
td = 20 s
Pulse Waveform
0
10
20
30
40
50
60
70
80
90
100
110
0
25
50
75
100
125
150
Ambient Temperature - TA (oC)
Power Derating Curve
Clamping Voltage vs. Peak Pulse Current
0
2
4
6
8
10
12
0
1
2
3
4
5
6
Peak Pulse Current - IPP (A)
Waveform
Parameters
tr = 8µs
td = 20µ
S



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