 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
CY7C024AV Datasheet(PDF) 1 Page - Cypress Semiconductor |
|
|
|||||||||||||||||||||||||||||
CY7C024AV Datasheet(HTML) 1 Page - Cypress Semiconductor |
|
|
1 / 20 page  CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-06052 Rev. *M Revised March 30, 2011 Features ■ True dual-ported memory cells which enable simultaneous access of the same memory location ■ 4, 8 or 16K × 16 organization ■ (CY7C024AV/024BV [1]/ 025AV/026AV) ■ 4 or 8K × 18 organization (CY7C0241AV/0251AV) ■ 16K × 18 organization (CY7C036AV) ■ 0.35 micron CMOS for optimum speed and power ■ High speed access: 20 and 25 ns ■ Low operating power ❐ Active: ICC = 115 mA (typical) ❐ Standby: ISB3 = 10 A (typical) ■ Fully asynchronous operation ■ Automatic power down ■ Expandable data bus to 32 bits, 36 bits or more using Master and Slave chip select when using more than one device ■ On chip arbitration logic ■ Semaphores included to permit software handshaking between ports ■ INT flag for port-to-port communication ■ Separate upper byte and lower byte control ■ Pin select for Master or Slave (M/S) ■ Commercial and industrial temperature ranges ■ Available in 100-pin Pb-free TQFP and 100-pin TQFP Notes 1. CY7C024AV and CY7C024BV are functionally identical. 2. IO8–IO15 for x16 devices; IO9–IO17 for x18 devices. 3. IO0–IO7 for x16 devices; IO0–IO8 for x18 devices. 4. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices. 5. BUSY is an output in master mode and an input in slave mode. R/WL OEL IO8/9L–IO15/17L IO Control Address Decode A0L–A11/12/13L CEL OEL R/WL BUSYL IO Control CEL Interrupt Semaphore Arbitration SEML INTL M/S UBL LBL IO0L–IO7/8L R/WR OER IO8/9L–IO15/17R CER UBR LBR IO0L–IO7/8R UBL LBL A0L–A11/1213L True Dual-Ported RAM Array A0R–A11/12/13R CER OER R/WR BUSYR SEMR INTR UBR LBR Address Decode A0R–A11/12/13R [2] [2] [3] [3] [5] [5] 12/13/14 8/9 8/9 12/13/14 8/9 8/9 12/13/14 12/13/14 [4] [4] [4] [4] Logic Block Diagram [+] Feedback |
Similar Part No. - CY7C024AV |
|
Similar Description - CY7C024AV |
|
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
