DS26514GN datasheet(2/305 Pages) MAXIM

2 / 305 page

DS26514 4-Port T1/E1/J1 Transceiver

19-5856; Rev 4; 5/11

2 of 305

TABLE OF CONTENTS

DETAILED DESCRIPTION.................................................................................................9

FEATURE HIGHLIGHTS ..................................................................................................10

2.1

GENERAL................................................................................................................................... 10

2.2

LINE INTERFACE ......................................................................................................................... 10

2.3

CLOCK SYNTHESIZERS ............................................................................................................... 10

2.4

JITTER ATTENUATOR .................................................................................................................. 10

2.5

FRAMER/FORMATTER ................................................................................................................. 11

2.6

SYSTEM INTERFACE ................................................................................................................... 11

2.7

HDLC CONTROLLERS................................................................................................................. 12

2.8

TEST AND DIAGNOSTICS ............................................................................................................. 12

2.9

MICROCONTROLLER PARALLEL PORT .......................................................................................... 12

2.10

SLAVE SERIAL PERIPHERAL INTERFACE (SPI) FEATURES .......................................................... 12

APPLICATIONS ...............................................................................................................13

SPECIFICATIONS COMPLIANCE ...................................................................................14

ACRONYMS AND GLOSSARY .......................................................................................16

MAJOR OPERATING MODES.........................................................................................17

BLOCK DIAGRAMS .........................................................................................................18

PIN DESCRIPTIONS ........................................................................................................20

8.1

PIN FUNCTIONAL DESCRIPTION ................................................................................................... 20

FUNCTIONAL DESCRIPTION .........................................................................................28

9.1

PROCESSOR INTERFACE............................................................................................................. 28

9.1.1

SPI Serial Port Mode....................................................................................................................... 28

9.1.2

SPI Functional Timing Diagrams ..................................................................................................... 28

9.2

CLOCK STRUCTURE.................................................................................................................... 31

9.2.1

Backplane Clock Generation ........................................................................................................... 31

9.2.2

CLKO Output Clock Generation ...................................................................................................... 32

9.3

RESETS AND POWER-DOWN MODES ........................................................................................... 33

9.4

INITIALIZATION AND CONFIGURATION ........................................................................................... 34

9.4.1

Example Device Initialization and Sequence ................................................................................... 34

9.5

GLOBAL RESOURCES.................................................................................................................. 34

9.6

PER-PORT RESOURCES.............................................................................................................. 34

9.7

DEVICE INTERRUPTS .................................................................................................................. 34

9.8

SYSTEM BACKPLANE INTERFACE ................................................................................................. 36

9.8.1

Elastic Stores.................................................................................................................................. 36

9.8.2

IBO Multiplexing.............................................................................................................................. 39

9.8.3

H.100 (CT Bus) Compatibility .......................................................................................................... 45

9.8.4

Transmit and Receive Channel Blocking Registers.......................................................................... 47

9.8.5

Transmit Fractional Support (Gapped Clock Mode) ......................................................................... 47

9.8.6

Receive Fractional Support (Gapped Clock Mode) .......................................................................... 47

9.9

FRAMERS................................................................................................................................... 48

9.9.1

T1 Framing ..................................................................................................................................... 48

9.9.2

E1 Framing ..................................................................................................................................... 51

9.9.3

T1 Transmit Synchronizer ............................................................................................................... 53

9.9.4

Signaling......................................................................................................................................... 54

9.9.5

T1 Data Link ................................................................................................................................... 59

9.9.6

E1 Data Link ................................................................................................................................... 61

9.9.7

Maintenance and Alarms................................................................................................................. 62

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