PCA9646

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© NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 1 — 1 March 2011

8 of 22

NXP Semiconductors

PCA9646

Buffered 4-channel 2-wire bus switch

[1]

Supply voltage dependent; refer to graphs (Figure 9 through Figure 12) for typical trend.

[2]

Guaranteed by design, not subject to test.

RESET

HIGH-level input voltage

2.0

-

-

V

4.8

-

-

V

LOW-level input voltage

-

-

650

mV

-

-

900

mV

hysteresis voltage

100

-

-

mV

200

-

-

mV

input leakage current

1-

+1

A

LOW-level reset time

[2] -25

-

ns

reset time

-

250

500

ns

power-on reset pulse time

-

250

500

ns

Address pins (A0, A1, A2)

HIGH-level input voltage

1.7

-

-

V

3.5

-

-

V

LOW-level input voltage

--0.7

V

--1.5

V

input leakage current

1-

+1

A

Timing characteristics (Figure 8)

delay time

-

100

-

ns

-

70

-

ns

fall time

-16

-

ns

Table 4.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Fig 8.

Timing diagram

002aaf438

time

SDx, SCx input

SDx, SCx output