PCF8593 datasheet(13/35 Pages) NXP

13 / 35 page

PCF8593

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 04 — 6 October 2010

13 of 35

NXP Semiconductors

PCF8593

Low power clock and calendar

In the 50 Hz clock mode or event-counter mode the oscillator is disabled and the oscillator

input is switched to a high-impedance state. This allows the user to feed the 50 Hz

reference frequency or an external high speed event signal into the input OSCI.

7.10.1 Designing

When designing the printed-circuit board layout, keep the oscillator components as close

to the IC package as possible, and keep all other signal lines as far away as possible. In

applications involving tight packing of components, shielding of the oscillator may be

necessary. AC coupling of extraneous signals can introduce oscillator inaccuracy.

7.11 Initialization

Note that immediately following power-on, all internal registers are undefined and,

following a RESET pulse on pin 3, must be defined via software. Attention should be paid

to the possibility that the device may be initially in event-counter mode, in which event the

oscillator will not operate. Over-ride can be achieved via software.

Reset is accomplished by applying an external RESET pulse (active LOW) at pin 3. When

reset occurs only the I2C-bus interface is reset. The control and status register and all

clock counters are not affected by RESET. RESET must return HIGH during device

operation.

An RC combination can also be utilized to provide a power-on RESET signal at pin 3. In

this event, the values of the PCF8593 must fulfil the following relationship to guarantee

power-on reset (see Figure 13).

RESET input must be input must be

≤ 0.3V

DD when VDD reaches VDD(min) (or higher).

It is recommended to set the stop counting flag of the control and status register before

loading the actual time into the counters. Loading of illegal states may lead to a temporary

clock malfunction.

To avoid overload of the internal diode by falling VDD, an external diode should be added in parallel

to RR if CR ≥ 0.2 μF. Note that RC must be evaluated with the actual VDD of the application, as their

value will be VDD rise-time dependent.

Fig 13. PCF8593 reset

RESET

PCF8593

VDD

013aaa388

VDD

reset

input

PCF8593 Datasheet(PDF) 13 Page - NXP Semiconductors

PCF8593 Datasheet(HTML) 13 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Datasheet Download

Link URL