LH28F008SA datasheet(13/27 Pages) SHARP

13 / 27 page

8M (1M × 8) Flash Memory

LH28F008SA

Figure 5. Automated Byte Write Flowchart

START

BUS

OPERATION

COMMAND

COMMENTS

WRITE 40H (10H),

BYTE ADDRESS

WRITE BYTE

ADDRESS/DATA

WSM

READY?

YES

FULL STATUS

CHECK IF DESIRED

BYTE WRITE

COMPLETED

BYTE WRITE

SUCCESSFUL

VPP RANGE

ERROR

BYTE WRITE

ERROR

STATUS REGISTER

DATA READ

(see above)

SR.3 = 0

SR.4 = 0

Write

Standby/Read

Byte Write

Setup

Byte Write

Data = 40H (10H)

Addr = Byte to be written

Data to be written

Addr = Byte to be written

Check RY/BY

VOH = Ready, VOL = Busy

Repeat for subsequent bytes.

Full status check can be done after each byte or after a

sequence of bytes.

Write FFH after the last byte write operation to reset the

device to Read Array Mode.

Read Status Register

Check SR.7

1 = Ready, 0 = Busy

Toggle OE or CE to update

Status Register

BUS

OPERATION

COMMAND

FULL STATUS CHECK PROCEDURE

COMMENTS

Optional

Read

Standby

CPU may already have read

Status Register data in WSM

Ready polling above

Check SR.3

1 = VPP Low Detect

Check SR.4

1 = Byte Write Error

SR.3 must be cleared, if set during a byte write attempt,

before further attempts are allowed by the Write State

Machine.

SR.4 is only cleared by the Clear Status Register Command,

in cases where multiple bytes are written before full status is

checked.

If error is detected, clear the Status Register before

attempting retry or other error recovery.

28F008SA-5

LH28F008SA Datasheet(PDF) 13 Page - Sharp Corporation

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