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RM48L950 Datasheet(PDF) 49 Page - Texas Instruments |
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RM48L950 Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 157 page  tf tr VCCIO VOH VOH VOL VOL 0 Output RM48L950 RM48L750 RM48L550 www.ti.com SPNS174 – SEPTEMBER 2011 Table 3-4. Switching Characteristics for Output Timings versus Load Capacitance (CL) (continued) Parameter MIN MAX Unit Rise time, tr 4mA low EMI pins CL = 15 pF 5.6 ns (see Table 3-2) CL = 50 pF 10.4 CL = 100 pF 16.8 CL = 150 pF 23.2 Fall time, tf CL = 15 pF 5.6 ns CL= 50 pF 10.4 CL = 100 pF 16.8 CL = 150 pF 23.2 Rise time, tr 2mA-z low EMI pins CL = 15 pF 8 ns (see Table 3-2) CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 Fall time, tf CL = 15 pF 8 ns CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 Rise time, tr Selectable 8mA / 2mA-z 8mA mode CL = 15 pF 2 ns pins CL = 50 pF 4 (see Table 3-2) CL = 100 pF 8 CL = 150 pF 11 Fall time, tf CL = 15 pF 2 ns CL = 50 pF 4 CL = 100 pF 8 CL = 150 pF 11 Rise time, tr 2mA-z mode CL = 15 pF 8 ns CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 Fall time, tf CL = 15 pF 8 ns CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 Figure 3-3. CMOS-Level Outputs Table 3-5. Timing Requirements for Outputs(1) Parameter MIN MAX UNIT td(parallel_out) Delay between low to high, or high to low transition of general-purpose output signals 5 ns that can be configured by an application in parallel, e.g. all signals in a GIOA port, or all N2HET1 signals, etc. (1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check Table 3-2 for output buffer drive strength information on each signal. Copyright © 2011, Texas Instruments Incorporated Device Operating Conditions 49 Submit Documentation Feedback focus.ti.com: RM48L950 RM48L750 RM48L550 |
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