LSM303DLMTR datasheet(23/38 Pages) STMICROELECTRONICS

23 / 38 page

LSM303DLM

Doc ID 018725 Rev 1

23/38

The device contains a set of registers which are used to control its behavior and to retrieve

acceleration data. The register address, made up of 7 bits, is used to identify them and to

write the data through the serial interface.

9.1

Linear acceleration register description

9.1.1

CTRL_REG1_A (20h)

PM bits allow selection between power-down and two operating active modes. The device is

in power-down mode when the PD bits are set to “000” (default value after boot). Table 18

shows all the possible power mode configurations and respective output data rates. Output

data in the low-power modes are computed with a low-pass filter cut-off frequency defined

by DR1 and DR0 bits.

DR bits, in normal-mode operation, select the data rate at which acceleration samples are

produced. In low-power mode they define the output data resolution. Table 19 shows all the

possible configurations for the DR1 and DR0 bits.

Table 16.

CTRL_REG1_A register

PM2

PM1

PM0

DR1

DR0

Zen

Yen

Xen

Table 17.

CTRL_REG1_A description

PM2 - PM0

Power mode selection. Default value: 000

(000: power-down; others: refer to

Table 18)

DR1, DR0

Data rate selection. Default value: 00

(00:50 Hz; others: refer to

Table 19)

Zen

Z axis enable. Default value: 1

(0: Z axis disabled; 1: Z axis enabled)

Yen

Y axis enable. Default value: 1

(0: Y axis disabled; 1: Y axis enabled)

Xen

X axis enable. Default value: 1

(0: X axis disabled; 1: X axis enabled)

Table 18.

Power mode and low-power output data rate configurations

PM2

PM1

PM0

Power mode selection

Output data rate [Hz]

ODRLP

Power-down

Normal mode

ODR

Low-power

0.5

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