12-Bit, 300ksps ADCs

with FIFO and Internal Reference

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13

True Differential Analog Input T/H

The equivalent circuit of Figure 3 shows the

MAX11626–MAX11629/MAX11632/MAX11633’s input

architecture. In track mode, a positive input capacitor is

connected to AIN0–AIN15. A negative input capacitor is

connected to GND. For external T/H timing, use clock

mode 01. After the T/H enters hold mode, the difference

between the sampled positive and negative input volt-

ages is converted. The time required for the T/H to

acquire an input signal is determined by how quickly its

input capacitance is charged. If the input signal’s

source impedance is high, the required acquisition time

time needed for a signal to be acquired, plus the

power-up time. It is calculated by the following equa-

tion:

device. The varying power-up times are detailed in the

less than 1.4µs, and any source impedance below 300

Ω

does not significantly affect the ADC’s AC performance.

A high-impedance source can be accommodated either

between the positive and negative analog inputs.

Internal FIFO

The MAX11626–MAX11629/MAX11632/MAX11633 con-

tain a FIFO buffer that can hold up to 16 ADC results.

This allows the ADC to handle multiple internally clocked

conversions, without tying up the serial bus. If the FIFO is

filled and further conversions are requested without

reading from the FIFO, the oldest ADC results are over-

written by the new ADC results. Each result contains 2

bytes, with the MSB preceded by four leading zeros.

After each falling edge of CS, the oldest available byte of

data is available at DOUT, MSB first. When the FIFO is

empty, DOUT is zero.

Internal Clock

The MAX11626–MAX11629/MAX11632/MAX11633 oper-

ate from an internal oscillator, which is accurate within

10% of the 4.4MHz nominal clock rate. The internal

oscillator is active in clock modes 00, 01, and 10. Read

out the data at clock speeds up to 10MHz. See Figures

4–7 for details on timing specifications and starting a

conversion.

Applications Information

Register Descriptions

The MAX11626–MAX11629/MAX11632/MAX11633 com-

municate between the internal registers and the exter-

nal circuitry through the SPI-/QSPI-compatible serial

interface. Table 1 details the registers and the bit

names. Tables 2–5 show the various functions within

the conversion register, setup register, averaging regis-

ter, and reset register.

Conversion Time Calculations

The conversion time for each scan is based on a num-

ber of different factors: conversion time per sample,

samples per result, results per scan, and if the external

reference is in use.

Use the following formula to calculate the total conver-

sion time for an internally timed conversion in clock

modes 00 and 10 (see the

Electrical Characteristics

section as applicable):

where

determined by the number of channels being

scanned or by NSCAN1, NSCAN0.

nal reference is already powered up or external ref-

erence is being used .

In clock mode 01, the total conversion time depends on

how long CNVST is held low or high, including any time

required to turn on the internal reference. Conversion

time in externally clocked mode (CKSEL1, CKSEL0 = 11)

depends on the SCLK period and how long CS is held

high between each set of eight SCLK cycles. In clock

mode 01, the total conversion time does not include the

time required to turn on the internal reference.

REGISTER NAME

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Conversion

1

CHSEL3

CHSEL2

CHSEL1

CHSEL0

SCAN1

SCAN0

X

Setup

0

1

CKSEL1

CKSEL0

REFSEL1

REFSEL0

X

X

Averaging

0

0

1

AVGON

NAVG1

NAVG0

NSCAN1

NSCAN0

Reset

0001

RESET

XX

X

Table 1. Input Data Byte (MSB First)

X = Don’t care.