COMMERCIALTEMPERATURERANGE

IDTCV152

PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR

13

PD ASSERTION

PD

CPU 133MHz

CPU# 133MHz

SRC 100MHz

SRC# 100MHz

USB 48MHz

PCI 33MHz

REF 14.31818

PCI STOP FUNCTIONALITY

If PCIF (2:0) and SRC clocks are set to be free-running through SMBus programming, they will ignore the PCI_STOP register bit.

PCI_STOP

CPU

CPU#

SRC

SRC#

PCIF/PCI

USB

DOT96

DOT96#

REF

(Byte 6 bit 3)

1

Normal

Normal

Normal

Normal

33MHz

48MHz

Normal

Normal

14.318MHz

0

Normal

Normal

Low

Low

48MHz

Normal

Normal

14.318MHz

PD, POWER DOWN

PD is an asynchronous active high input used to shut off all clocks cleanly prior to clock power. When PD is asserted high all clocks will be driven low before

turning off the VCO. In PD de-assertion all clocks will start without glitches.

PD

CPU

CPU#

SRC

SRC#

PCIF/PCI

USB

REF

0

Normal

Normal

Normal

Normal

33MHz

48MHz

14.318MHz

Float

Float

Low

Low

Low