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20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373

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10

10 - 21

HMC795LP5E

v00.0409

SiGe Wideband direct Quadrature

Modulator w/ vGa, 50 - 2800 MHz

3. HMC795lP5e registers the data bits in the next 29 rising edges of sClK (total of 30 data bits). the

lsBs of the data bits represent the address of the register that is intended to be read.

4. Host places the 7 register address bits on the next 7 falling edges of sClK (MsB to lsB) while the

HMC795lP5e reads the address bits on the corresponding rising edge of sCK. For a read operation this

is “0000000”.

5. Host places the 3 chip address bits <100> on the next 3 falling edges of sCK (MsB to lsB). Note

the HMC795lP5e chip address is fixed as “4d” or “100b”.

6. seN goes from low to high after the 40th rising edge of sCK. this completes the first portion of the

ReAd cycle.

7. the host asserts seN (active low serial Port enable) followed by a rising edge sClK.

8. HMC795lP5e places the 30 data bits, 7 address bits, and 3 chip id bits on the sdO on each rising

edge of the sCK commencing with the first rising edge beginning with MsB.

9. the host de-asserts seN (i.e. sets seN high) after reading the 40 bits from the sdO output. the 32

bits consists of 30 data bits, 7 address bits, and the 3 chip id bits. this completes the ReAd cycle.

Figure 8. SPI Timing Diagram for write and read operation

Parameter

Conditions

Min.

Typ.

Max

Units

seN to sCK setup time

8

nsec

sdi to sCK setup time

8

nsec

sdi to ClK hold time

8

nsec

sCK high duration

8

nsec

sCK low duration

8

nsec

seN low duration after 40th ClK

20

nsec

seN high duration

20

nsec