GS9068 SD SDI Cable Driver

Data Sheet

22213 - 4

August 2010

10 of 11

6. Package and Ordering Information

6.1 Package Dimensions

Figure 6-1: Package Dimensions

6.2 Ordering Information

7. Revision History

0.010

q2

L

DETAIL “A”

C

0.015 ±0.004 x 45°

DETAIL “A”

q1

B

A

A1

E

X

D

e

Pin 1

ID Mark

Gauge Plane

Seating Plane

NOTES:

1. All dimensions in inches unless otherwise stated.

2. Lead coplanarity should be 0 to 0.004” max.

3. Package surface finishing: VDI 24~27 (dual).

Package surface finishing: VDI 13~15 (16L SOIC[NB] matrix).

4. All dimensions exclude mold flashes.

5. The lead width (B) to be determined at 0.0075”

from the lead tip.

8 SOIC

Min.

Max.

A

A1

B

D

E

H

e

C

L

X

q2

q1

0.054

0.068

0.004

0.0098

0.014

0.019

0.189

0.196

0.157

0.244

0.229

0.150

0.050 BSC

0.0075

0.0098

0.016

0.034

0.0215 REF

0°

8°

7° BSC

Part Number

Package

Temperature Range

Pb-free and Green

GS9068-CKAE3

8 pin SOIC

0°C to 70°C

Yes

GS9068-CTAE3

8 pin SOIC Tape

0°C to 70°C

Yes

Version

ECR

PCN

Date

Changes And/or Modifications

A

120608

–

July 2002

New document.

B

125775

–

July 2002

Added detailed block descriptions and initial applications

information.

0

127024

–

December 2002

Document upgraded to Preliminary Data Sheet and AC/DC

Characteristics edited to match current design specification limits.

1

128544

–

March 2003

Document upgraded to Data Sheet.

2

133977

–

June 2004

Added lead-free and green information.

3

139114

38124

January 2006Corrected Input Differential Swing to 2200mV.

4

154753

–

August 2010

Corrected Package Dimensions and Ordering Information.