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GS9092ACNE3 Datasheet(PDF) 39 Page - Gennum Corporation

Part # GS9092ACNE3
Description  GenLINX III 270Mb/s Serializer for SDI and DVB-ASI
PDF  63 Pages
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Manufacturer  GENNUM [Gennum Corporation]
Direct Link  http://www.gennum.com
Logo GENNUM - Gennum Corporation

GS9092ACNE3 Datasheet(HTML) 39 Page - Gennum Corporation

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GS9092A GenLINX® III 270Mb/s Serializer for SDI and
DVB-ASI
Data Sheet
34715 - 4
May 2010
39 of 63
Table 3-4: Host Interface Description for Internal Processing Disable Register
Register Name
Bit
Name
Description
R/W
Default
IOPROC_DISABLE
Address: 00h
15-10
–
Not Used
––
9ANC_PKT_INS
Ancillary Packet Insertion Enable. When the FIFO is
configured for ancillary data insertion, set HIGH to
begin inserting ancillary data.
NOTE: Setting ANC_PKT_INS LOW will not
automatically disable ancillary data insertion (see
Ancillary Data Insertion on page 32).
R/W
0
8-7
FIFO_MODE[1:0]
FIFO Mode: These bits control which mode the
internal FIFO is operating in (see Table 3-2)
R/W
0
6
H_CONFIG
Horizontal sync timing output configuration. Set LOW
for active line blanking timing. Set HIGH for H
blanking based on the H bit setting of the TRS word.
See Figure 3-8 in HVF Timing Signal Inputs on page 35.
R/W
0
5
352M_CALCSMPTE 352M Calculation. When set LOW, the
GS9092A will automatically generate packet
information prior to insertion. When set HIGH, the
user must program the VIDEO_FORMAT registers with
the SMPTE 352M packet to be inserted.
R/W
–
4
352M_INSSMPTE 352M Packet Insertion. The IOPROC_EN pin
and SMPTE_BYPASS pin must also be set HIGH. Set
HIGH to disable.
NOTE: The user should disable Packet Insertion when
serializing SDTI signals.
R/W
–
3
ILLEGAL_REMAP
Illegal code re-mapping. Detection and correction of
illegal code words within the active picture area. The
IOPROC_EN pin and SMPTE_BYPASS pin must also be
set HIGH. Set HIGH to disable.
R/W
0
2
EDH_CRC_INS
Error Detection & Handling (EDH) Cyclical Redundancy
Check (CRC) error insertion. The GS9092A will
generate and insert EDH packets. The IOPROC_EN pin
and SMPTE_BYPASS pin must also be set HIGH. Set
HIGH to disable.
R/W
0
1ANC_CSUM_INS
Ancillary Data Checksum insertion. The IOPROC_EN
pin and SMPTE_BYPASS pin must also be set HIGH. Set
HIGH to disable.
R/W
0
0TRS_INS
Timing Reference Signal Insertion. Occurs only when
IOPROC_EN pin and SMPTE_BYPASS pin is HIGH. Set
HIGH to disable.
R/W
0



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