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Atmel LED Drivers-MSL1061/MSL1064

Note 1. All parameters are tested at T

Note 2. Minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if either SDA or SCL is held low for

t

Note 3. t

Note 4. t

Note 5. A master device must internally provide an SDA hold time of at least 300ns to ensure an SCL low state

Note 6. The maximum SDA and SCL rise times is 300ns. The maximum SDA fall time is 250ns. This allows series protection resistors to be

connected between SDA and SCL inputs and the SDA/SCL bus lines without exceeding the maximum allowable rise time

Note 7. MSL1061/64 includes input filters on SDA, SCL, and AD0 inputs that suppress noise less than 50ns

Note 8. Subject to thermal dissipation characteristics of the device

Note 9. When mounted according to JEDEC JEP149 and JESD51-12 for a two-layer PCB,

θ

Note 10. Guaranteed by design and characterization. Not production tested

Note 11. STR0 to STR5 current matching is the difference of any one string current and the average of all string currents divided by the average of

all string currents

Note 12. The MSL1061/64 selects the string (STR0 through STR5) with the lowest voltage to control the boost regulator voltage

PARAMETER

SYMBOL

CONDITIONS AND NOTES

MIN

TYP

MAX

UNIT

I²C SWITCHING CHARACTERISTICS

SCL clock frequency

1/t

SCL

TOEN bit D1=0 in control

register to disable bus

timeout

0

1000

kHz

TOEN bit D1=1 in control

register to enable bus

timeout

0.066

Bus time-out period

t

TIMEOUT

15

25

ms

STOP to START condition bus

free time

t

BUF

0.5

µs

Repeated START condition

hold time

t

HD:STA

0.26

µs

Repeated START condition

set-up time

t

SU:STA

0.26

µs

STOP condition set-up time

t

SU:STOP

0.26

µs

SDA data hold time

t

HD:DAT

5

ns

SDA data valid acknowledge time

t

VD:ACK

(Note 3)

0.05

0.55

µs

SDA data valid time

t

VD:DAT

(Note 4)

0.05

0.55

µs

SDA data set-up time

t

SU:DAT

100

ns

SCL clock low period

t

LOW

0.5

µs

SCL clock high period

t

HIGH

0.26

µs

SDA, SCL fall time

t

F

(Note 5, Note 6)

120

ns

SDA, SCL rise time

t

R

120

ns

SDA, SCL input suppression

filter period

t

SP

(Note 7, Note 10)

50

ns

Atmel LED Drivers-MSL1061/MSL1064

6-string PWM LED Driver with Digitally Compensated, 1.1MHz,