FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.)

Rev. 1.1

June 2011

Page 2 of 12

Address

Latch

1K x 64

FRAM Array

Data Latch

8

SDA

Counter

Serial to Parallel

Converter

Control Logic

SCL

WP

A0-A2

Figure 1. FM24CL64B Block Diagram

Pin Description

Pin Name

Type

Pin Description

A0-A2

Input

Device Select Address 0-2: These pins are used to select one of up to 8 devices of

the same type on the same two-wire bus. To select the device, the address value on

the two pins must match the corresponding bits contained in the slave address. The

address pins are pulled down internally.

SDA

I/O

Serial Data/Address: This is a bi-directional pin for the two-wire interface. It is

open-drain and is intended to be wire-OR‟d with other devices on the two-wire bus.

The input buffer incorporates a Schmitt trigger for noise immunity and the output

driver includes slope control for falling edges. An external pull-up resistor is

required.

SCL

Input

Serial Clock: The serial clock pin for the two-wire interface. Data is clocked out of

the part on the falling edge, and into the device on the rising edge. The SCL input

also incorporates a Schmitt trigger input for noise immunity.

WP

Input

Write Protect: When tied to VDD, addresses in the entire memory map will be write-

protected. When WP is connected to ground, all addresses may be written. This pin

is pulled down internally.

VDD

Supply

Supply Voltage

VSS

Supply

Ground