FM31T372 datasheet(19/26 Pages) RAMTRON

19 / 26 page

FM31T372/374/376/378-G

Rev. 1.1

Apr. 2011

Page 19 of 26

Selective (Random) Read

There is a simple technique that allows a user to

select a random address location as the starting point

for a read operation. This involves using the first

three bytes of a write operation to set the internal

address followed by subsequent read operations.

To perform a selective read, the bus master sends out

the slave address with the LSB set to 0. This specifies

a write operation. According to the write protocol,

the bus master then sends the address bytes that are

loaded into the internal address latch. After the

FM31T37x acknowledges the address, the bus master

issues a Start condition. This simultaneously aborts

the write operation and allows the read command to

be issued with the slave address LSB set to a 1. The

operation is now a read from the current address.

Read operations are illustrated below.

RTC /Companion Write Operation

All RTC and Companion writes operate in a similar

manner to memory writes. The distinction is that a

different device ID is used and only one byte address

is needed instead of two. Figure 16 illustrates a single

byte write to this device.

RTC/Companion Read Operation

As with writes, a read operation begins with the

Slave Address. To perform a register read, the bus

master supplies a Slave Address with the LSB set to

1. This indicates that a read operation is requested.

After receiving the complete Slave Address, the

FM31T37x will begin shifting data out from the

current

address

the

clock.

Auto-increment operates for the special function

registers as with the memory address. A current

address read for the registers look exactly like the

memory except that the device ID is different.

The FM31T37x contains two separate address

registers, one for the memory address and the other

for the register address. This allows the contents of

one address register to be modified without affecting

the current address of the other register. For example,

this would allow an interrupted read to the memory

while still providing fast access to an RTC register. A

subsequent memory read will then continue from the

memory address where it previously left off, without

requiring the load of a new memory address.

However, a write sequence always requires an

address to be supplied.

Slave Address

Data Byte

By Master

By FM31xxx

Start

Address

Stop

Acknowledge

Data

Figure 14. Current Address Memory Read

Slave Address

Data Byte

By Master

By FM31xxx

Start

Address

Stop

Acknowledge

Data

Data Byte

Acknowledge

Figure 15.

Sequential Memory Read

By FM31T37x

FM31T372 Datasheet(PDF) 19 Page - Ramtron International Corporation

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