LNK623 datasheet(5/18 Pages) POWERINT

5 / 18 page

Rev. E 09/09

LNK623-626

www.powerint.com

Output Regulation

The LNK626 regulates the output using ON/OFF control,

enabling or disabling switching cycles based on the sampled

voltage on the FEEDBACK pin. The output voltage is sensed

using a primary referenced winding on transformer T1 eliminating

the need for an optocoupler and a secondary sense circuit. The

resistor divider formed by R3 and R6 feeds the winding voltage

into U1. Standard 1% resistor values were used to center the

nominal output voltages. Resistor R5 and C5 reduce pulse

grouping by creating an offset voltage that is proportional to the

number of consecutive enabled switching cycles.

Key Application Considerations

Output Power Table

The data sheet maximum output power table (Table 1)

represents the maximum practical continuous output power

level that can be obtained in a Flyback converter under the

following assumed conditions:

1. The minimum DC input voltage is 100 V or higher at 90 VAC

input. The value of the input capacitance should be large

enough to meet these criteria for AC input designs.

2. Secondary output of 5 V with a Schottky rectiﬁer diode.

3. Assumed efﬁciency of 80%.

4. Continuous conduction mode operation (K

P = 0.4).

5. Reﬂected Output Voltage (V

OR) of 110 V.

6. The part is board mounted with SOURCE pins soldered to a

sufﬁcient area of copper to keep the SOURCE pin tempera-

ture at or below 110 °C for P package and 100 °C for D

packaged devices.

7. Ambient temperature of 50 °C for open frame designs and

an internal enclosure temperature of 60 °C for adapter

designs.

Note: Higher output power are achievable if the efﬁciency is

higher than 80%, typically for high output voltage designs.

Bypass Pin Capacitor

A 1 μF Bypass pin capacitor (C4) is recommended. The

capacitor voltage rating should be equal to or greater than

6.8 V. The capacitor’s dielectric material is not important. The

capacitor must be physically located close to the

LinkSwitch-CV BYPASS pin.

Circuit board layout

LinkSwitch-CV is a highly integrated power supply solution that

integrates on a single die, both the controller and the high

voltage MOSFET. The presence of high switching currents and

voltages together with analog signals makes it especially

important to follow good PCB design practice to ensure stable

and trouble free operation of the power supply.

When designing a board for the LinkSwitch-CV based power

supply, it is important to follow the following guidelines:

Single Point Grounding

Use a single point (Kelvin) connection at the negative terminal of

the input ﬁlter capacitor for the LinkSwitch-CV SOURCE pin and

bias winding return. This improves surge capabilities by

returning surge currents from the bias winding directly to the

input ﬁlter capacitor.

Bypass Capacitor

The BYPASS pin capacitor should be located as close as

possible to the SOURCE and BYPASS pins.

Feedback Resistors

Place the feedback resistors directly at the FEEDBACK pin of

the LinkSwitch-CV device. This minimizes noise coupling.

Thermal Considerations

The copper area connected to the source pins provide the

LinkSwitch-CV heat sink. A rule of thumb estimate is that the

LinkSwitch-CV will dissipate 10% of the output power. Provide

enough copper area to keep the source pin temperature below

110° C to provide margin for part to part R

DS(ON) variation.

Secondary Loop Area

To minimize leakage inductance and EMI, the area of the loop

connecting the secondary winding, the output diode and the

output ﬁlter capacitor should be minimized. In addition,

sufﬁcient copper area should be provided at the anode and

cathode terminal of the diode for heatsinking. A larger area is

preferred at the quiet cathode terminal. A large anode area can

increase high frequency radiated EMI.

Electrostatic Discharge Spark Gap

In chargers and adapters ESD discharges may be applied to

the output of the supply. In these applications the addition of a

spark gap is recommended. A trace is placed along the

isolation barrier to form one electrode of a spark gap. The other

electrode, on the secondary side, is formed by the output return

node. The arrangement directs ESD energy from the secondary

to the primary side AC input. A 10 mil gap is placed near the

AC input. The gap decouples any noise picked up on the spark

gap trace to the AC input. The trace from the AC input to the

spark gap electrode should be spaced away from other traces

to prevent unwanted arcing occurring and possible circuit

damage.

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