LC877696B/80B/64B/48B

No.A0965-21/25

UART (Full Duplex) Operating Conditions at Ta = -20 to +70°C, VSS1 = VSS2 = VSS3 = 0V

Specification

Parameter

Symbol

Pin/Remarks

Conditions

VDD[V]

min

typ

max

unit

Transfer rate

UBR

UTX(P00),

URX(P01)

2.2 to 5.5

16/3

8192/3

tCYC

Data length: 7/8/9 bits (LSB first)

Stop bits:

1 bit (2-bit in continuous data transmission mode)

Parity bits:

None

Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H)

Example of 8-bit Data Reception Mode Processing (Receive Data=55H)

* When using UART, set P0LDDR (P0DDR: BIT0) to “0”

Characteristics of a Sample Main System Clock Oscillation Circuit

Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a

SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values

with which the oscillator vendor confirmed normal and stable oscillation.

Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator

Circuit Constant

Oscillation

Stabilization Time

Nominal

Frequency

Vendor

Name

Oscillator Name

C1

[pF]

C2

[pF]

Rf1

[

Ω]

Rd1

[

Ω]

Operating

Voltage

Range

[V]

typ

[ms]

max

[ms]

Remarks

12MHz

MURATA

CSTCE120G52-R0

(10)

(10)

OPEN

330

3.0 to 5.5

0.05

0.15

Built-in

C1, C2

CSTLS8M00G53-B0

(15)

(15)

OPEN

680

2.5 to 5.5

0.05

0.15

8MHz

MURATA

CSTCE8M00G52-R0

(10)

(10)

OPEN

330

2.5 to 5.5

0.05

0.15

Built-in

C1, C2

CSTLS4M00G53-B0

(15)

(15)

OPEN

1.5k

2.2 to 5.5

0.05

0.15

4MHz

MURATA

CSTCR4M00G53-R0

(15)

(15)

OPEN

1k

2.5 to 5.5

0.05

0.15

Built-in

C1, C2

The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD

goes above the operating voltage lower limit (see Figure 4).

Transmit data (LSB first)

Start of

transmission

End of

transmission

UBR

Start bit

Stop bit

UBR

Receive data (LSB first)

Start of

reception

End of

reception

Start bit

Stop bit