Pad Assignment

Chip size: 3255

´ 3050 (mm)

2

* The IC substrate should be connected to VSS in the PCB layout artwork.

Pad Coordinates

Unit:

mm

Pad No.

X

Y

Pad No.

X

Y

Pad No.

X

Y

1

-1379.40

1407.45

35

-336.80

-1310.40

69

1512.50

593.85

2

-1512.50

956.25

36

-233.40

-1310.40

70

1512.50

688.85

3

-1512.50

861.25

37

-125.00

-1310.40

71

1512.50

783.85

4

-1512.50

766.25

38

-28.00

-1310.40

72

1512.50

878.85

5

-1512.50

671.25

39

77.60

-1310.40

73

1512.50

973.85

6

-1512.50

576.25

40

172.60

-1310.40

74

1512.50

1068.85

7

-1512.50

481.25

41

295.20

-1310.40

75

1512.50

1163.85

8

-1512.50

386.25

42

408.80

-1310.40

76

1512.50

1258.85

9

-1512.50

291.25

43

522.40

-1310.40

77

1512.50

1353.85

10

-1512.50

196.25

44

636.00

-1310.40

78

995.60

1407.45

HT1647A

Rev. 1.40

3

April 29, 2011

PATENTED

( 0 , 0 )

1

1 0 2 1 0 1 1 0 0

7 8

7 9

8 0

8 1

8 2

8 3

8 4

8 5

8 6

8 7

8 8

8 9

9 0

9 1

9 2

9 3

9 4

9 5

9 6

9 7

9 8

9 9

2

3

4

5

6

7

8

9

1 0

1 1

1 2

1 3

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

2 3

2 4

2 5

2 6

2 7

2 8

2 9

3 0

3 1

3 2

3 3

3 4

3 5

3 6

3 7

3 8

3 9

4 0

4 1

4 2

4 4

4 3

4 5

4 6

4 7

4 8

4 9

5 0

5 1

5 2

7 7

7 6

7 5

7 4

7 3

7 2

7 1

7 0

6 9

6 8

6 7

6 6

6 5

6 4

6 3

6 2

6 1

6 0

5 9

5 8

5 7

5 6

5 5

5 4

5 3

S E G 4 3

S E G 4 4

S E G 4 5

S E G 4 6

S E G 4 7

S E G 4 8

S E G 4 9

S E G 5 0

S E G 5 1

S E G 5 2

S E G 5 3

S E G 5 4

S E G 5 5

S E G 5 6

S E G 5 7

S E G 5 8

S E G 5 9

S E G 6 0

S E G 6 1

S E G 6 2

S E G 6 3

C S

R D

W R

S E G 1 6

S E G 1 5

S E G 1 4

S E G 1 3

S E G 1 2

S E G 1 1

S E G 1 0

S E G 9

S E G 8

S E G 7

S E G 6

S E G 5

S E G 4

S E G 3

S E G 2

S E G 1

S E G 0

C O M 1 5

C O M 1 4

C O M 1 3

C O M 1 2

C O M 1 1

C O M 1 0

C O M 9

C O M 8