AM1808 datasheet(101/262 Pages) TI

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AM1808

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SPRS653C

– FEBRUARY 2010 – REVISED DECEMBER 2011

Table 5-21. Timing Requirements for EMIFA Asynchronous Memory Interface (1)

1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

READS and WRITES

tc(CLK)

Cycle time, EMIFA module clock

6.75

tw(EM_WAIT)

Pulse duration, EM_WAIT assertion and deassertion

READS

tsu(EMDV-EMOEH)

Setup time, EM_D[15:0] valid before EM_OE high

th(EMOEH-EMDIV)

Hold time, EM_D[15:0] valid after EM_OE high

Setup Time, EM_WAIT asserted before end of Strobe

tsu (EMOEL-EMWAIT)

4E+3

Phase(2)

WRITES

Setup Time, EM_WAIT asserted before end of Strobe

tsu (EMWEL-EMWAIT)

4E+3

Phase(2)

(1)

E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when

SYSCLK3 is selected and set to 100MHz, E=10ns

(2)

Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended

wait states. Figure 5-14 and Figure 5-15 describe EMIF transactions that include extended wait states inserted during the STROBE

phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where

the HOLD phase would begin if there were no extended wait cycles.

Peripheral Information and Electrical Specifications

101

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