AM1808 datasheet(106/262 Pages) TI

106 / 262 page

AM1808

SPRS653C

– FEBRUARY 2010 – REVISED DECEMBER 2011

www.ti.com

5.11 DDR2/mDDR Controller

The DDR2/mDDR Memory Controller is a dedicated interface to DDR2/mDDR SDRAM. It supports JESD79-2A standard compliant DDR2 SDRAM

devices and compliant Mobile DDR SDRAM devices.

The DDR2/mDDR Memory Controller support the following features:

•

JESD79-2A standard compliant DDR2 SDRAM

•

Mobile DDR SDRAM

•

512 MByte memory space for DDR2

•

256 MByte memory space for mDDR

•

CAS latencies:

– DDR2: 2, 3, 4 and 5

– mDDR: 2 and 3

•

Internal banks:

– DDR2: 1, 2, 4 and 8

– mDDR:1, 2 and 4

•

Burst length: 8

•

Burst type: sequential

•

1 chip select (CS) signal

•

Page sizes: 256, 512, 1024 and 2048

•

SDRAM autoinitialization

•

Self-refresh mode

•

Partial array self-refresh (for mDDR)

•

Power down mode

•

Prioritized refresh

•

Programmable refresh rate and backlog counter

•

Programmable timing parameters

•

Little endian

106

Peripheral Information and Electrical Specifications

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