AM1808 datasheet(189/262 Pages) TI

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MII_RXCLK(Input)

MII_RXD[3]-MII_RXD[0],

MII_RXDV,MII_RXER(Inputs)

MII_TCLK(Input)

MII_TXD[3]-MII_TXD[0],

MII_TXEN(Outputs)

AM1808

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SPRS653C

– FEBRUARY 2010 – REVISED DECEMBER 2011

Table 5-100. Timing Requirements for EMAC MII Receive 10/100 Mbit/s(1) (see Figure 5-47)

1.3V, 1.2V, 1.1V, 1.0V

NO.

PARAMETER

UNIT

MIN

MAX

tsu(MRXD-MII_RXCLKH)

Setup time, receive selected signals valid before MII_RXCLK high

th(MII_RXCLKH-MRXD)

Hold time, receive selected signals valid after MII_RXCLK high

(1)

Receive selected signals include: MII_RXD[3]-MII_RXD[0], MII_RXDV, and MII_RXER.

Figure 5-47. EMAC Receive Interface Timing

Table 5-101. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit

10/100 Mbit/s(1) (see Figure 5-48)

1.3V, 1.2V,

1.0V

1.1V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

td(MII_TXCLKH-

Delay time, MII_TXCLK high to transmit selected signals valid

MTXD)

(1)

Transmit selected signals include: MTXD3-MTXD0, and MII_TXEN.

Figure 5-48. EMAC Transmit Interface Timing

Peripheral Information and Electrical Specifications

189

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