LIS302DL

Mechanical and electrical specifications

13/42

2.3.2

Subject to general operating conditions for Vdd and Top.

Table 6.

Figure 4.

1.

2.

A device must internally provide an hold time of at least 300ns for the SDA signal (referred to VIHmin of the SCL signal) to

bridge the undefined region of the falling edge of SCL

3.

Cb = total capacitance of one bus line, in pF

4.

Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both port

Symbol

Parameter

Unit

Min

Max

Min

Max

SCL clock frequency

0

100

0

400

KHz

SCL clock low time

4.7

1.3

µs

SCL clock high time

4.0

0.6

SDA setup time

250

100

ns

SDA data hold time

0

0

µs

SDA and SCL rise time

1000

(3)

300

ns

SDA and SCL fall time

300

(3)

300

START condition hold time

4

0.6

µs

Repeated START condition

setup time

4.7

0.6

STOP condition setup time

4

0.6

Bus free time between STOP

and START condition

4.7

1.3

SDA

SCL

START

REPEATED

START

STOP

START