ICS8705 datasheet(11/18 Pages) IDT

11 / 18 page

8705BY

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REV. H JULY 2, 2010

ICS8705

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL

CLOCK GENERATOR

FIGURE 3C. CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 3B.

CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 3D.

CLK/NCLK INPUT DRIVEN BY

3.3V LVDS DRIVER

3.3V

Zo = 50 Ohm

LVPECL

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

3.3V

Input

Zo = 50 Ohm

Input

HiPerClockS

CLK

nCLK

3.3V

125

Zo = 50 Ohm

3.3V

125

LVPECL

3.3V

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both V

SWING and VOH must meet

the V

PP and VCMR input requirements.

Figures 3A to 3D show

interface examples for the CLK/nCLK input driven by the most

common driver types. The input interfaces suggested here are

FIGURE 3A. CLK/NCLK INPUT DRIVEN BY

LVHSTL DRIVER

examples only. Please consult with the vendor of the driver

component to confirm the driver termination requirements. For

example in

Figure 4A, the input termination applies for LVHSTL

drivers. If you are using an LVHSTL driver from another ven-

dor, use their termination recommendation.

1.8V

Input

LVHSTL Driver

ICS

HiPerClockS

LVHSTL

3.3V

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

Zo = 50 Ohm

100

3.3V

LVDS_Driv er

Zo = 50 Ohm

Receiv er

CLK

nCLK

3.3V

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