701J—01/25/10

ICS952601

21

The following diagrams illustrate SRC clock timing during PCI_Stop# and PwrDwn# modes with SRC_Pwrdwn and

SRC_Stop tristate control bits set to driven or tristate in byte 2 of the control register.

SRC_Stop = Driven, SRC_Pwrdwn = Driven

PCI_Stop#

1.8mS

PWRDWN#

PCI (Free Running)

CPU (Free Running)

CPU# (Free Running)

SRC (Stoppable)

SRC# (Stoppable)

1 PCI

clock max

Notes:

1. When both bits (SRC_Stop & SRC_Pwrdown tristate bits) are set to driven, the clock chip will never tristate the SRC output

clock (assuming clock's OE bit is set to "1")

SRC Clock Tristate Timing

SRC_Stop = Tristate, Pwrdwn = Tristate

PCI_Stop#

1.8mS

PWRDWN#

PCI (Free Running)

CPU (Free Running)

CPU# (Free Running)

SRC (Stoppable)

SRC# (Stoppable)

1 PCI

clock max

Notes:

1. When SRC_Stop and SRC_Pwrdwn bits are set to tristate, the clock chip will tristate outputs during the assertion of

PCI_Stop# and PWRDWN#.

2. Tristate outputs are pulled low by output termination resistors as shown here.