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5

5 - 4

DIS

CO

NTIN

UE

D

PR

OD

UC

T

No

t Reco

mm

ended

for

Ne

w D

esi

gns

Truth Table

Serial Control Input

Attenuation

Setting

RF1 - RF2

C 0.5

C 1

C 2

C 4

C 8

High

High

High

High

High

Reference

I.L.

Low

High

High

High

High

0.5 dB

High

Low

High

High

High

1 dB

High

High

Low

High

High

2 dB

High

High

High

Low

High

4 dB

High

High

High

High

Low

8 dB

Low

Low

Low

Low

Low

15.5 dB

Max. Atten.

Any combination of the above states will provide an attenuation

approximately equal to the sum of the bits selected.

Worst Case Step Error

Between Successive Attenuation States

-1.2

-0.8

-0.4

0

0.4

0.8

1.2

0.5

1

1.5

2

2.5

3

3.5

4

FREQUENCY (GHz)

Digital Control Voltages

State

Vcc = +5V

Vcc = +3V

Low

0 to 1.3V

0 to 0.7V

High

3.5 to 5V

2.3 to 3V

Parameter

Symbol

Vcc = +5V

Vcc = +3V

Units

Min.

Max.

Min.

Max.

Serial Input Setup

Time

ts

20

-

100

-

ns

Hold time from Serial

Input to Shift Clock

th

0

-

5

-

ns

Setup time from

Shift Clock to Latch

Enable

tlsup

40

-

100

-

ns

Propagation delay,

Latch Enable to C0.5

through C8

tpd

-

30

-

70

ns

Setup time from

Reset to Shift Clock

-20

-

50

-

ns

Clock Frequency

(1/tclk)

fclk

-

30

-

10

MHz

Timing

Timing Diagram

Serial Input Truth Table

Latch

Enable

Shift

Clock

Reset

Function

X

X

L

Shift register cleared

X



H

Shift register clocked



XH

Contents of shift register

transferred to Digital

Attenuator

HMC305LP4 / 305LP4E

v03.0809

0.5 dB LSB GaAs MMIC 5-BIT SERIAL

CONTROL DIGITAL ATTENUATOR, 0.7 - 3.8 GHz