HT46RU232 datasheet(13/60 Pages) HOLTEK

13 / 60 page

HT46RU232

Rev. 1.00

April 23, 2008

Reset

There are three ways in which a reset may occur:

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

The WDT time-out during HALT differs from other chip

reset conditions, for it can perform a

²warm reset² that

resets only the program counter and stack pointer,

leaves the other circuits at their original state. Some reg-

isters remain unaffected during any other reset condi-

tions. Most registers are reset to the

²initial condition²

when the reset conditions are met. Examining the

PDF and TO flags, the program can distinguish between

different

²chip resets².

PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES wake-up HALT

WDT time-out during normal operation

WDT wake-up HALT

Note:

²u² stands for ²unchanged²

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem awakes from the HALT state or during power up.

Awaking from the HALT state or system power up an

SST delay is added. An extra SST delay is added during

power up period, and any wake-up from HALT may en-

able only the SST delay. The functional unit chip reset

status are shown below.

Program Counter

000H

Interrupt

Disable

Prescaler, Divider

Cleared

WDT

Clear. After master reset,

WDT begins counting

Timer/event Counter

Off

Input/output Ports

Input mode

Stack Pointer

Points to the top of the stack

Timer/Event Counter

Two Timer/Event Counters (TMR0,TMR1) are imple-

mented in the microcontroller. The timer/event counter 0

contains an 16-bit programmable count-up counter and

the clock may come from an external source or an inter-

nal clock source. An internal clock source comes from

fSYS. The timer/event counter 1 contains an 16-bit pro-

grammable count-up counter and the clock may come

from an external source or an internal clock source. An

internal clock source comes from fSYS/4. The external

clock input allows the user to count external events,

measure time intervals or pulse widths, or to generate

an accurate time base.

There are six registers related to the Timer/Event Coun-

ter 0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH) and

the Timer/Event Counter 1; TMR1H (0FH), TMR1L

(10H), TMR1C (11H). Writing TMR0L (TMR1L) will only

put the written data to an internal lower-order byte buffer

(8-bit) and writing TMR0H (TMR1H) will transfer the

specified data and the contents of the lower-order byte

buffer to TMR0H (TMR1H) and TMR0L (TMR1L) regis-

ters, respectively. The Timer/Event Counter 1/0 preload

operations. Reading TMR0H (TMR1H) will latch the

contents of TMR0H (TMR1H) and TMR0L (TMR1L)

counters to the destination and the lower-order byte

buffer, respectively. Reading the TMR0L (TMR1L) will

read the contents of the lower-order byte buffer. The

TMR0C (TMR1C) is the Timer/Event Counter 0 (1) con-

trol register, which defines the operating mode, counting

enable or disable and an active edge.

W a r m R e s e t

W D T

H A L T

C o l d

R e s e t

R E S

P o w e r - o n D e t e c t i o n

S S T

1 0 - b i t R i p p l e

C o u n t e r

O S C 1

W D T

E x t e r n a l

T i m e - o u t

R e s e t

Reset Configuration

t S S T + t O P D

R E S

V D D

S S T T i m e - o u t

C h i p R e s e t

Reset Timing Chart

R E S

V D D

1 0 0 k W

1 0 k W

0 . 0 1 m F

R E S

V D D

1 0 0 k W

0 . 1 m F

B a s i c

R e s e t

C i r c u i t

H i - n o i s e

R e s e t

C i r c u i t

Reset Circuit

Note:

Most applications can use the Basic Reset Cir-

cuit as shown, however for applications with

extensive noise, it is recommended to use the

Hi-noise Reset Circuit.

HT46RU232 Datasheet(PDF) 13 Page - Holtek Semiconductor Inc

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