HT67F50 datasheet(66/242 Pages) HOLTEK

66 / 242 page

Rev. 1.50

March 06 , 2012

Rev. 1.50

March 06 , 2012

HT67F30/HT67F40/HT67F50/HT67F60

TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPRO

SLOW Mode to NORMAL Mode Switching

In SLOW Mode the system uses either the LXT or LIRC low speed system oscillator. To switch

back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should

be set to "1" or HLCLK bit is "0", but CKS2~CKS0 is set to "010", "011", "100", "101", "110" or

"111". As a certain amount of time will be required for the high frequency clock to stabilise, the

status of the HTO bit is checked. The amount of time required for high speed system oscillator

stabilization depends upon which high speed system oscillator type is used.

Entering the SLEEP0 Mode

There is only one way for the device to enter the SLEEP0 Mode and that is to execute the "HALT"

instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the

WDT and LVD both off. When this instruction is executed under the conditions described above, the

following will occur:

● The system clock, WDT clock and Time Base clock will be stopped and the application program

will stop at the "HALT" instruction.

● The Data Memory contents and registers will maintain their present condition.

● The WDT will be cleared and stopped no matter if the WDT clock source originates from the fSUB

clock or from the system clock.

● The I/O ports will maintain their present conditions.

● In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,

will be cleared.

Entering the SLEEP1 Mode

There is only one way for the device to enter the SLEEP1 Mode and that is to execute the "HALT"

instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the

WDT or LVD on. When this instruction is executed under the conditions described above, the

following will occur:

● The system clock and Time Base clock will be stopped and the application program will stop at

the "HALT" instruction, but the WDT or LVD will remain with the clock source coming from the

fSUB clock.

● The Data Memory contents and registers will maintain their present condition.

● The WDT will be cleared and resume counting if the WDT clock source is selected to come from

the fSUB clock as the WDT is enabled.

● The I/O ports will maintain their present conditions.

● In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,

will be cleared.

HT67F50 Datasheet(PDF) 66 Page - Holtek Semiconductor Inc