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HT83050 Datasheet(PDF) 12 Page - Holtek Semiconductor Inc |
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HT83050 Datasheet(HTML) 12 Page - Holtek Semiconductor Inc |
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12 / 40 page  HT83XXX Rev. 1.60 12 November 19, 2008 Address RAM Mapping Read/Write Description 00H IAR0 R/W Indirect Addressing Register 0 01H MP0 R/W Memory Pointer 0 05H ACC R/W Accumulator 06H PCL R/W Program counter lower-order byte address 07H TBLP R/W Table pointer lower-order byte register 08H TBLH R Table higher-order byte content register 09H WDTS R/W Watchdog Timer option setting register 0AH STATUS R/W Status register 0BH INTC R/W Interrupt control register 0 0DH TMR0 R/W Timer Counter 0 register 0EH TMR0C R/W Timer Counter 0 control register 10H TMR1 R/W Timer Counter 1 register 11H TMR1C R/W Timer Counter 1 control register 12H PA R/W Port A I/O data register 13H PAC R/W Port A I/O control register 14H PB R/W Port B I/O data register 15H PBC R/W Port B I/O control register 18H LATCH0H R/W Voice ROM address latch 0 [A17, A16] 19H LATCH0M R/W Voice ROM address latch 0 [A15~A8] 1AH LATCH0L R/W Voice ROM address latch 0 [A7~A0] 26H PWMCR R/W PWM control register 27H PWML R/W, higher-nibble available only PWM output data P3~P0 to PWML7~PWML4 28H PWMH R/W PWM output data P11~P4 to PWMH7~PWMH0 29H VOL R/W, higher-nibble available only Volume control register and volume controlled by VOL8~VOL4 2AH LATCHD R Voice ROM data register 2BH~2FH Unused 30H~7FH User data RAM R/W User data RAM Note: R: Read only W: Write only R/W: Read/Write Interrupts The HT83XXX provides two 8-bit programmable timer interrupts, and a time base interrupt. The Interrupt Con- trol registers (INTC:0BH) contain the interrupt control bits to set to enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all other inter- rupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain in- terrupt needs servicing within the service routine, the EMI bit and the corresponding INTC bit may be set to al- low interrupt nesting. If the stack is full, the interrupt re- quest will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decre- mented. If immediate service is desired, the stack must be prevented from becoming full. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack and then branching to subroutines at the specified location(s) in the program memory. Only the program counter is pushed onto the stack. The programmer must save the contents of the register or status register (STATUS) in advance if they are altered by an interrupt service pro- gram which corrupts the desired control sequence. |
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