Rev.A Dec.2010

Copyright@Winsemi Microelectronics Co., Ltd., All right reserved.

S

S

S

SF

F

F

FF

F

F

F73

73

73

730

0

0

0

S

S

S

Siiiilllliiiic

c

c

co

o

o

on

n

n

n N

N

N

N----Ch

Ch

Ch

Cha

a

a

an

n

n

nn

n

n

nel

el

el

el M

M

M

MOS

OS

OS

OSF

F

F

FET

ET

ET

ET

Features

■ Ultra-low Gate Charge(Typical 32nC)

■ Fast Switching Capability

■ 100%Avalanche Tested

■ Maximum Junction Temperature Range(150℃)

General Description

Th i s Po w e r MOS F ET is pr o d uc e d usi n g Wi n s e m i ’ s ad v a n c e d

planar stripe, DMOS technology. This latest technology has been

especially designed to minimize on-state resistance, have a high

rugg ed ava lan ch e cha racteris tic s. This devices is spe cially well

suited for high efficiency switch model power supplies, power factor

correction and half bridge and full bridge resonant topology line a

electronic lamp ballast.

Absolute Maximum Ratings

Symbol

Parameter

Value

Units

Drain Source Voltage

400

V

Continuous Drain Current(@Tc=25℃)

5.5*

A

Continuous Drain Current(@Tc=100℃)

2.9*

A

Drain Current Pulsed

(Note1)

22*

A

Gate to Source Voltage

±30

V

Single Pulsed Avalanche Energy

(Note 2)

330

mJ

Repetitive Avalanche Energy

(Note 1)

7.4

mJ

dv/dt

Peak Diode Recovery dv/dt

(Note 3)

4

V/ns

Total Power Dissipation(@Tc=25℃)

38

W

Derating Factor above 25℃

0.3

W/℃

Junction and Storage Temperature

-55~150

℃

300

℃

*Drain current limited by maximum junction temperature

Thermal Characteristics

Symbol

Parameter

Value

Units

Min

Typ

Max

Thermal Resistance, Junction-to-Case

-

-

3.3

℃/W

Thermal Resistance, Junction-to-Ambient

-

-

62

℃/W