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AFS090 Datasheet(PDF) 235 Page - Microsemi Corporation |
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AFS090 Datasheet(HTML) 235 Page - Microsemi Corporation |
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235 / 334 page  Fusion Family of Mixed Signal FPGAs R e visio n 2 2 - 219 Output Register Timing Characteristics Figure 2-138 • Output Register Timing Diagram Preset Clear DOUT CLK Data_out Enable tOSUE 50% 50% tOSUD tOHD 50% 50% tOCLKQ 1 0 tOHE tORECPRE tOREMPRE tORECCLR tOREMCLR tOWCLR tOWPRE tOPRE2Q tOCLR2Q tOCKMPWH tOCKMPWL 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% Table 2-177 • Output Data Register Propagation Delays Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tOCLKQ Clock-to-Q of the Output Data Register 0.59 0.67 0.79 ns tOSUD Data Setup Time for the Output Data Register 0.31 0.36 0.42 ns tOHD Data Hold Time for the Output Data Register 0.00 0.00 0.00 ns tOSUE Enable Setup Time for the Output Data Register 0.44 0.50 0.59 ns tOHE Enable Hold Time for the Output Data Register 0.00 0.00 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.80 0.91 1.07 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.80 0.91 1.07 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.22 0.25 0.30 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.22 0.25 0.30 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.22 0.25 0.30 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.22 0.25 0.30 ns tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register 0.36 0.41 0.48 ns tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register 0.32 0.37 0.43 ns Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. |
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