AFS090 datasheet(247/334 Pages) MICROSEMI

247 / 334 page

Fusion Family of Mixed Signal FPGAs

R e visio n 2

2 - 231

Boundary Scan

Fusion devices are compatible with IEEE Standard 1149.1, which defines a hardware architecture and

the set of mechanisms for boundary scan testing. The basic Fusion boundary scan logic circuit is

composed of the test access port (TAP) controller, test data registers, and instruction register (Figure 2-

144 on page 2-232). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST,

SAMPLE/PRELOAD, and BYPASS) and the optional IDCODE instruction (Table 2-185 on page 2-232).

Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input),

TDI, TDO (test data input and output), TMS (test mode selector), and TRST (test reset input). TMS, TDI,

and TRST are equipped with pull-up resistors to ensure proper operation when no input data is supplied

to them. These pins are dedicated for boundary scan test usage. Refer to the "JTAG Pins" section on

page 2-228 for pull-up/-down recommendations for TDO and TCK pins. The TAP controller is a 4-bit state

machine (16 states) that operates as shown in Figure 2-144 on page 2-232. The 1s and 0s represent the

values that must be present on TMS at a rising edge of TCK for the given state transition to occur. IR and

DR indicate that the instruction register or the data register is operating in that state.

The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals

for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset

state. To guarantee a reset of the controller from any of the possible states, TMS must remain High for

five TCK cycles. The TRST pin can also be used to asynchronously place the TAP controller in the Test-

Logic-Reset state.

Fusion devices support three types of test data registers: bypass, device identification, and boundary

scan. The bypass register is selected when no other register needs to be accessed in a device. This

speeds up test data transfer to other devices in a test data path. The 32-bit device identification register

is a shift register with four fields (LSB, ID number, part number, and version). The boundary scan register

observes and controls the state of each I/O pin. Each I/O cell has three boundary scan register cells,

each with a serial-in, serial-out, parallel-in, and parallel-out pin.

The serial pins are used to serially connect all the boundary scan register cells in a device into a

boundary scan register chain, which starts at the TDI pin and ends at the TDO pin. The parallel ports are

connected to the internal core logic I/O tile and the input, output, and control ports of an I/O buffer to

capture and load data into the register to control or observe the logic state of each I/O.

Table 2-184 • TRST and TCK Pull-Down Recommendations

VJTAG

Tie-Off Resistance*

VJTAG at 3.3 V

200

Ω to 1 kΩ

VJTAG at 2.5 V

200

Ω to 1 kΩ

VJTAG at 1.8 V

500

Ω to 1 kΩ

VJTAG at 1.5 V

500

Ω to 1 kΩ

Note:

*Equivalent parallel resistance if more than one device is on JTAG chain.

AFS090 Datasheet(PDF) 247 Page - Microsemi Corporation

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