AFS090 datasheet(255/334 Pages) MICROSEMI

255 / 334 page

Fusion Family of Mixed Signal FPGAs

R e visio n 2

3 -5

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every Fusion device. These circuits

ensure easy transition from the powered off state to the powered up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In addition, the

I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 3-1

on page 3-6.

There are five regions to consider during power-up.

Fusion I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 3-1).

2. VCCI > VCC – 0.75 V (typical).

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically

built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

•

During programming, I/Os become tristated and weakly pulled up to VCCI.

•

JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

3. Output buffers, after 200 ns delay from input buffer activation

PLL Behavior at Brownout Condition

Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-

up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout

activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 3-1 on page 3-6

for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels

(0.75 V ± 0.25 V), the PLL output lock signal goes low and/or the output clock is lost.

Table 3-5 • FPGA Programming, Storage, and Operating Limits

Product

Grade

Storage

Temperature

Element

Grade Programming

Cycles

Retention

Commercial

Min. TJ = 0°C

FPGA/FlashROM

500

20 years

Max. TJ = 85°C

Embedded Flash

< 1,000

20 years

< 10,000

10 years

< 15,000

5 years

Industrial

Min. TJ = –40°C

FPGA/FlashROM

500

20 years

Max. TJ = 100°C

Embedded Flash

< 1,000

20 years

< 10,000

10 years

< 15,000

5 years

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