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AFS090 Datasheet(PDF) 269 Page - Microsemi Corporation |
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AFS090 Datasheet(HTML) 269 Page - Microsemi Corporation |
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269 / 334 page ![]() Fusion Family of Mixed Signal FPGAs R e visio n 2 3 - 19 Applicable to Advanced I/O Banks Single-Ended 3.3 V LVTTL/LVCMOS 3.3 – 16.69 2.5 V LVCMOS 2.5 – 5.12 1.8 V LVCMOS 1.8 – 2.13 1.5 V LVCMOS (JESD8-11) 1.5 – 1.45 3.3 V PCI 3.3 – 18.11 3.3 V PCI-X 3.3 – 18.11 Differential LVDS 2.5 2.26 1.20 LVPECL 3.3 5.72 1.87 Applicable to Standard I/O Banks 3.3 V LVTTL/LVCMOS 3.3 – 16.79 2.5 V LVCMOS 2.5 – 5.19 1.8 V LVCMOS 1.8 – 2.18 1.5 V LVCMOS (JESD8-11) 1.5 – 1.52 Table 3-12 • Summary of I/O Input Buffer Power (per pin)—Default I/O Software Settings (continued) VCCI (V) Static Power PDC7 (mW)1 Dynamic Power PAC9 (µW/MHz)2 Notes: 1. PDC7 is the static power (where applicable) measured on VCCI. 2. PAC9 is the total dynamic power measured on VCC and VCCI. |
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