IXDN0036 datasheet(12/41 Pages) IXYS

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Ballast Demonstrator Operation

ATAVRFBKIT / EVLD001 User Guide

4-11

7597A–AVR–02/06

The PFC ON time is modified proportionally to the error between 380V and the actual

value of the bus. In case the Vbus reaches the overshoot value of 410V the pulse is

reduced to 0.

This control loop will determine the regulation response to ripple current on the 380V

bulk filter cap and the loads for a specific application design requirements.

4.3.1

System Sequential

Step Description

Main voltage applied.

Undervoltage lockout (UVLO) released.

IXI859 voltage regulator supplies 3.3V to microcontroller.

Power microcontroller ON in low current standby mode.

Disable ½ bridge drive output PB0 & PB1

Disable PD5 comparator (Not implemented).

PB7, scaled haversine voltage must be >0.848 Vmin (90VAC) & <2.497 (265VAC)

Vmax (haversine peak) for the PFC to start.

-Check AC line condition every 200 mS maximum (10 cycles of 50 Hz).

-If the check fails, halt PD0, PB0, PB1 and set line voltage alarm high or low. Do not

restart until line within specs to protect PFC.

PD0 soft start PFC with 10µS pulses at 50µS period for 800µS.

Monitor comparator at PD7 for change 1 to 0 indicating a zero crossing of the

PFC inductor secondary voltage. This occurs after the 10µS start pulse burst.

If no PD7 change and after 800µS halt PD0, wait 1 second and provide PD0

with 10µS pulses for 800µS. Try 10 times and if no crossing, set PFC alarm.

After PD7 comparator transition and 380VDC (2.368V at PB2), enable PFC control loop.

-Set PB2 (380VDC sense) setpoint to 2.368V with deadband.

-If PB2 > 2.50V then inhibit PD0 pulse.

-If PB2 = < 2.368V then use the control loop to establish the PD0 PFC pulse width.

Limit pulse width to 25uS or as determined by the haversine peak voltage.

After PD0 PFC pulse, wait until PD0 = 0 & PD7 = 0 (PD0 off time) then enable

PD0 pulse according to table of error from setpoint.

-If PB2 (380V sense) > A/D 255 = overshoot.

When PB7 < 0.100V, limit PD0 minimum to 5 µS to reduce distortion at havers-

ine zero

crossover.

4.4

Lamp Operation

Description

T4 primary and C11 form a serial resonant circuit driven by the output half bridge. Since

the output is between 380V and 0V, DC isolation is provided by C14 to drive the lamp

circuit with AC. The lamp is placed across the resonating capacitor C11. The lamp fila-

ments are driven by windings on T1 secondaries to about 3Vrms so that the resonating

inductor current provides the starting lamp filament current.

IXDN0036 Datasheet(PDF) 12 Page - IXYS Corporation

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