AD5064 datasheet(8/36 Pages) AD

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AD5750/AD5750-1/AD5750-2

Data Sheet

Rev. D | Page 8 of 36

TIMING CHARACTERISTICS

AVDD/AVSS = ±12 V (± 10%) to ±24 V (± 10%), DVCC = 2.7 V to 5.5 V, GND = 0 V. VOUT: RLOAD = 2 kΩ, CL = 200 pF, IOUT: RLOAD =

300 Ω. All specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter1, 2

Limit at TMIN, TMAX

Unit

Description

ns min

SCLK cycle time

ns min

SCLK high time

ns min

SCLK low time

ns min

SYNC falling edge to SCLK falling edge setup time

ns min

16th SCLK falling edge to SYNC rising edge (on 24th SCLK falling edge if using PEC)

ns min

Minimum SYNC high time (write mode)

ns min

Data setup time

ns min

Data hold time

t9, t10

1.5

µs max

CLEAR pulse low/high activation time

t11

ns min

Minimum SYNC high time (read mode)

t12

ns max

SCLK rising edge to SDO valid (SDO CL = 15 pF)

t13

ns min

RESET pulse low time

Guaranteed by characterization, but not production tested.

All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

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