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Data Sheet

AD7988-1/AD7988-5

Rev. B | Page 17 of 24

VOLTAGE REFERENCE INPUT

The AD7988-x voltage reference input, REF, has a dynamic

input impedance and should therefore be driven by a low

impedance source with efficient decoupling between the REF

and GND pins, as explained in the Layout section.

When REF is driven by a very low impedance source, for example,

a reference buffer using the AD8031 or the AD8605, a ceramic

chip capacitor is appropriate for optimum performance.

If an unbuffered reference voltage is used, the decoupling value

depends on the reference used. For example, a 22 µF (X5R,

1206 size) ceramic chip capacitor is appropriate for optimum

performance using a low temperature drift ADR43x reference.

If desired, a reference-decoupling capacitor value as small as

2.2 µF can be used with a minimal impact on performance,

especially DNL.

Regardless, there is no need for an additional lower value ceramic

decoupling capacitor (for example, 100 nF) between the REF

and GND pins.

POWER SUPPLY

The AD7988-x uses two power supply pins: a core supply, VDD,

and a digital input/output interface supply, VIO. VIO allows

direct interface with any logic between 1.8 V and 5.0 V. To

reduce the number of supplies needed, VIO and VDD can be

tied together. The AD7988-x is independent of power supply

sequencing between VIO and VDD. Additionally, it is very

insensitive to power supply variations over a wide frequency

range, as shown in Figure 33.

FREQUENCY (kHz)

100

Figure 33. PSRR vs. Frequency

To ensure optimum performance, VDD should be roughly half

of REF, the voltage reference input. For example, if REF is 5.0 V,

VDD should be set to 2.5 V (±5%). If REF = 2.5V, and VDD =

2.5 V, performance is degraded as can be seen in Table 2.

The AD7988-x powers down automatically at the end of each

conversion phase.

DIGITAL INTERFACE

Although the AD7988-x has a reduced number of pins, it offers

flexibility in its serial interface modes.

The AD7988-x, when in CS mode, is compatible with SPI, QSPI™,

and digital hosts. This interface can use either a 3-wire or 4-wire

interface. A 3-wire interface using the CNV, SCK, and SDO

signals minimizes wiring connections and is useful, for

instance, in isolated applications. A 4-wire interface using the

SDI, CNV, SCK, and SDO signals allows CNV, which initiates

the conversions, to be independent of the readback timing

(SDI). This is useful in low jitter sampling or simultaneous

sampling applications.

The AD7988-x, when in chain mode, provides a daisy-chain

feature using the SDI input for cascading multiple ADCs on a

single data line, similar to a shift register.

The mode in which the part operates depends on the SDI level

when the CNV rising edge occurs. CS mode is selected if SDI is

high, and chain mode is selected if SDI is low. The SDI hold

time is such that when SDI and CNV are connected together,

the chain mode is selected.

The user must time out the maximum conversion time prior to

readback.

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