AD9653 datasheet(26/40 Pages) AD

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AD9653

Data Sheet

Rev. 0 | Page 26 of 40

Figure 65. Differential LVDS Sample Clock (Up to 1 GHz)

Figure 66. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

Input Clock Divider

The AD9653 contains an input clock divider with the ability

to divide the input clock by integer values between 1 and 8.

The AD9653 clock divider can be synchronized using the

external SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the

clock divider to be resynchronized on every SYNC signal or

only on the first SYNC signal after the register is written. A

valid SYNC causes the clock divider to reset to its initial state.

This synchronization feature allows multiple parts to have their

clock dividers aligned to guarantee simultaneous input sampling.

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a vari-

ety of internal timing signals and, as a result, may be sensitive to

clock duty cycle. Commonly, a ±5% tolerance is required on the

clock duty cycle to maintain dynamic performance characteristics.

The AD9653 contains a duty cycle stabilizer (DCS) that retimes

the nonsampling (falling) edge, providing an internal clock

signal with a nominal 50% duty cycle. This feature minimizes

performance degradation in cases where the clock input duty

cycle deviates from 50% greater than the specified ±5%. Noise and

distortion performance are nearly flat for a wider range of duty

cycles with the DCS on, as shown in Figure 67 and Figure 68.

Figure 67. SNR vs. DCS On/Off, VREF = 1.0 V

Figure 68. SNR vs. DCS On/Off, VREF = 1.3 V

Jitter in the rising edge of the input is still of concern and is not

easily reduced by the internal stabilization circuit. The duty

cycle control loop does not function for clock rates less than

20 MHz, nominally. The loop has a time constant associated

with it that must be considered in applications in which the

clock rate can change dynamically. A wait time of 1.5 µs to 5 µs

is required after a dynamic clock frequency increase or decrease

before the DCS loop is relocked to the input signal.

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency

(fA) due only to aperture jitter (tJ) can be calculated by

SNR Degradation = 20 log10













A t

In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter specifications. IF undersampling

applications are particularly sensitive to jitter (see Figure 69).

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9653.

Power supplies for clock drivers should be separated from the

0Ω

0.1µF

50kΩ

CLK–

CLK+

ADC

CLOCK

INPUT

CLOCK

INPUT

AD951x

LVDS DRIVER

OPTIONAL

100Ω

0.1µF

50Ω1

50Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

VCC

1kΩ

CLOCK

INPUT

AD951x

CMOS DRIVER

DUTY CYCLE (%)

SNRFS (DCS OFF)

SNRFS (DCS ON)

DUTY CYCLE (%)

SNRFS (DCS OFF)

SNRFS (DCS ON)

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