ADE7880ACPZ datasheet(90/104 Pages) AD

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ADE7880

Data Sheet

Rev. A| Page 90 of 104

Bit

Mnemonic

Default Value

Description

REVPSUM1

When this bit is set to 1, it indicates that the sum of all phase powers in the CF1 data

path has changed sign. The sign itself is indicated in Bit 3 (SUM1SIGN) of the PHSIGN

REVFRPA

When this bit is set to 1, it indicates that the Phase A fundamental reactive power

has changed sign. The sign itself is indicated in Bit 4 (AFVARSIGN) of the PHSIGN

REVFRPB

When this bit is set to 1, it indicates that the Phase B fundamental reactive power

has changed sign. The sign itself is indicated in Bit 5 (BFVARSIGN) of the PHSIGN

REVFRPC

When this bit is set to 1, it indicates that the Phase C fundamental reactive power

has changed sign. The sign itself is indicated in Bit 6 (CFVARSIGN) of the PHSIGN

REVPSUM2

When this bit is set to 1, it indicates that the sum of all phase powers in the CF2 data

path has changed sign. The sign itself is indicated in Bit 7 (SUM2SIGN) of the PHSIGN

CF1

When this bit is set to 1, it indicates a high-to-low transition has occurred at CF1 pin;

that is, an active low pulse has been generated. The bit is set even if the CF1 output

is disabled by setting Bit 9 (CF1DIS) to 1 in the CFMODE register. The type of power

used at the CF1 pin is determined by Bits[2:0] (CF1SEL[2:0]) in the CFMODE register

(see Table 44).

CF2

When this bit is set to 1, it indicates a high-to-low transition has occurred at the CF2

pin; that is, an active low pulse has been generated. The bit is set even if the CF2

output is disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE register. The type of

power used at the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0]) in the CFMODE

CF3

When this bit is set to 1, it indicates a high-to-low transition has occurred at CF3 pin;

that is, an active low pulse has been generated. The bit is set even if the CF3 output

is disabled by setting Bit 11 (CF3DIS) to 1 in the CFMODE register. The type of power

used at the CF3 pin is determined by Bits[8:6] (CF3SEL[2:0]) in the CFMODE register (see

Table 44).

DREADY

When this bit is set to 1, it indicates that all periodical (at 8 kHz rate) DSP

computations have finished.

REVPSUM3

When this bit is set to 1, it indicates that the sum of all phase powers in the CF3 data

path has changed sign. The sign itself is indicated in Bit 8 (SUM3SIGN) of the PHSIGN

HREADY

When this bit is set to 1, it indicates the harmonic block output registers have been

updated. If Bit 1 (HRCFG) in the HCONFIG register is cleared to 0, this flag is set to 1

every time the harmonic block output registers are updated at 8 kHz rate. If Bit

HRCFG is set to 1, the HREADY flag is set to 1 every time the harmonic block output

registers are updated at 8 kHz rate starting 750 ms after the harmonic block setup .

31:18

Reserved

0 0000 0000 0000

Reserved. These bits are always 0.

ADE7880ACPZ Datasheet(PDF) 90 Page - Analog Devices

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