ADIS16488SLASHPCBZ datasheet(29/36 Pages) AD

29 / 36 page

Data Sheet

ADIS16488

Rev. B | Page 29 of 36

SYSTEM CONTROLS

The ADIS16488 provides a number of system-level controls

for managing its operation, which include reset, self-test,

calibration, memory management, and I/O configuration.

GLOBAL COMMANDS

The GLOB_CMD register (see Table 114) provides trigger bits for

several operations. Write 1 to the appropriate bit in GLOB_CMD to

start a function. After the function completes, the bit restores to 0.

Table 114. GLOB_CMD (Page 3, Base Address = 0x02)

Bits

Description

Execution Time

[15:8]

Not used

Not applicable

Software reset

120 ms

Factory calibration restore

75 ms

[5:4]

Not used

Not applicable

Flash memory update

375 ms

Flash memory test

50 ms

Self-test

12 ms

Bias null

See Table 70

Software Reset

Turn to Page 3 (DIN = 0x8003) and then set GLOB_CMD[7] = 1

(DIN = 0x8280, DIN = 0x8300) to reset the operation, which

removes all data, initializes all registers from their flash settings,

and starts data collection. This function provides a firmware

alternative to the RST line (see Table 5, Pin 8).

Automatic Self-Test

Turn to Page 3 (DIN = 0x8003) and then set GLOB_CMD[1] = 1

(DIN = 0x8202, then DIN = 0x8300) to run an automatic self-

test routine, which executes the following steps:

1. Measure output on each sensor.

2. Activate self-test on each sensor.

3. Measure output on each sensor.

4. Deactivate the self-test on each sensor.

5. Calculate the difference with self-test on and off.

6. Compare the difference with internal pass/fail criteria.

7. Report the pass/fail results for each sensor in DIAG_STS.

After waiting 12 ms for this test to complete, turn to Page 0

(DIN = 0x8000) and read DIAG_STS using DIN = 0x0A00.

Note that using an external clock can extend this time. When

using an external clock of 100 Hz, this time extends to 35 ms.

Note that 100 Hz is too slow for optimal sensor performance.

MEMORY MANAGEMENT

The data retention of the flash memory depends on temperature

and the number of write cycles. Figure 25 characterizes the

dependence on temperature, and the FLSHCNT_LOW and

FLSHCNT_HIGH registers (see Table 115 and Table 116)

provide a running count of flash write cycles. The flash updates

every time GLOB_CMD[6], GLOB_CMD[3], or GLOB_CMD[0]

is set to 1.

Table 115. FLSHCNT_LOW (Page 2, Base Address = 0x7C)

Bits

Description

[15:0]

Binary counter; number of flash updates, lower word

Table 116. FLSHCNT_HIGH (Page 2, Base Address = 0x7E)

Bits

Description

[15:0]

Binary counter; number of flash updates, upper word

600

450

300

150

JUNCTION TEMPERATURE (°C)

100

125

135

150

Figure 25. Flash Memory Retention

Flash Memory Test

Turn to Page 3 (DIN = 0x8003), and then set GLOB_CMD[2] = 1

(DIN = 0x8204, DIN = 0x8300) to run a checksum test of the

internal flash memory, which compares a factory-programmed

value with the current sum of the same memory locations. The

result of this test loads into SYS_E_FLAG[6]. Turn to Page 0

(DIN = 0x8000) and use DIN = 0x0800 to read SYS_E_FLAG.

GENERAL-PURPOSE I/O

There are four general-purpose I/O lines: DIO1, DIO2, DIO3, and

DIO4. The FNCTIO_CTRL register controls the basic function

of each I/O line, which provides a number of useful functions.

Each I/O line will only support one function at a time. In cases

where a single line has two different assignments, the enable bit

for the lower-priority function will automatically reset to zero

and be disabled. The priority is (1) data-ready, (2) sync clock

input, (3) alarm indicator, and (4) general-purpose, where 1

identifies the highest priority and 4 indicates the lowest priority.

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