ADUCM361 datasheet(13/21 Pages) AD

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Preliminary Technical Data

ADuCM360/ADuCM361

Rev. Pr R| Page 13 of 21

SPI TIMING DIAGRAMS

Table 8. SPI Master Mode Timing

Parameter

Description

Min

Typ

Max

Unit

tSL

SCLK low pulse width1

(SPIDIV + 1) × tUCLK

tSH

SCLK high pulse width1

(SPIDIV + 1) × tUCLK

tDAV

Data output valid after SCLK edge

35.5

tDOSU

Data output setup before SCLK edge1

(SPIDIV + 1) ×

tUCLK

tDSU

Data input setup time before SCLK edge

58.7

tDHD

Data input hold time after SCLK edge

tDF

Data output fall time

35.5

tDR

Data output rise time

35.5

tSR

SCLK rise time

35.5

tSF

SCLK fall time

35.5

tUCLK = 62.5 ns. It corresponds to the internal 16MHz clock before the clock divider.

Figure 3. SPI Master Mode Timing (PHASE Mode = 1)

SCLK

(POLARITY = 0)

SCLK

(POLARITY = 1)

MOSI

MSB

BITS 6 TO 1

LSB

MISO

MSB IN

BITS 6 TO 1

LSB IN

tSH

tSL

tSR

tSF

tDR

tDF

tDAV

tDSU

tDHD

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